小弟最近在做课程设计，做sdram读取的时候用到pll进行倍频产生sdram时钟（100M），但是发现手头上的板子的sdram接口是普通io口，而专用的pll输出口却被sdram地址端占用了，用QII编译的时候报错说必须接到pll专用输出口，不知道有什么办法可以输出到普通io口。
请教了一位师兄，说可以试试通过把pll输出的那条路径约束为全局变量，但是还是会报错。
另外，我发现即使先不给sdram的时钟分配引脚，编译的时候也会报错说pll专用引脚被占用了（地址端），很是苦恼，希望有大神能够指点一下。
我的板子芯片是cyclone ep1c6Q240c8,专用pll输出脚在38,39。sdram_clk接在14脚。
下面是报错信息：
当pll分配到普通口时：
Error (186234): Can't place fast PLL "sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|pll" because I/O pin "sdram_clk" (port type EXTCLK of the PLL) is assigned to a location which is not connected to port type EXTCLK of any PLL on the device
不分配sdram_clk时：
Error (186252): Can't place fast PLL "sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|pll" in target device due to device constraints
Error (186253): Can't place fast PLL "sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|pll" in PLL location PLL_1 due to device constraints
Error (186262): Can't place fast PLL "sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|pll" in PLL location PLL_1 because the PLL I/O pin of port type EXTCLK (Pin_38) is already occupied by node "sdram_addr[3]"
Error (186263): Can't place fast PLL "sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|pll" in PLL location PLL_2 because I/O cell "clk_in" (port type INCLK of the PLL) is placed in an I/O pin (Pin_28) which cannot feed port type INCLK of PLL location PLL_2 |
楼主
标题置顶
标题高亮
