always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0) begin
uart_rxd_dly1 <= 1'b0;
uart_rxd_dly2 <= 1'b0;
uart_rxd_dly3 <= 1'b0;
uart_rxd_dly4 <= 1'b0;
end
else begin
uart_rxd_dly1 <= uart_rxd ;
uart_rxd_dly2 <= uart_rxd_dly1;
uart_rxd_dly3 <= uart_rxd_dly2;
uart_rxd_dly4 <= uart_rxd_dly3;
end
end
assign rxd_negdge_sig = (~uart_rxd_dly3) & uart_rxd_dly4; |
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