module RDC_AD_V20(clk,rst_n,ARM9200_WR,ARM9200_RD,ARM9200_nCS2,ARM9200_nCS6,ARM9200_DATA,ARM9200_ADDR,
sw,mcu_sclk,mcu_miso,mcu_mosi,mcu_npcs1,ad_rst,ad_sclk,ad_miso_a,ad_busy,ad_cs_n,
ad_convsta,da_rst,da_mosi,da_sclk,da_cs_n);
// 信号说明
input clk;
input rst_n;
input ARM9200_WR;
input ARM9200_RD;
input ARM9200_nCS2;
input ARM9200_nCS6;
inout [15:0] ARM9200_DATA;
input [15:0] ARM9200_ADDR;
input [1:0] sw;
input mcu_sclk;
output mcu_miso;
input mcu_mosi;
input mcu_npcs1;
output ad_rst;
output ad_sclk;
input ad_miso_a;
//input ad_miso_b;
input ad_busy;
output ad_cs_n;
output ad_convsta;
output da_rst;
//input da_miso;
output da_mosi;
output da_sclk;
output da_cs_n;
parameter DEVID = 4'h3;
/////////////////////////////////////////////////////////////////
reg ad_convsta_r;
reg ad_rst_r;
reg ad_cs_n_r;
reg da_cs_n_r;
reg da_rst_r;
reg ad_en_r;
reg da_en_r;
wire WR_CPLD,RD_CPLD,RD_DEVID;
reg [15:0] RD_DATA;
assign ad_sclk = mcu_sclk;
assign da_sclk = mcu_sclk;
assign mcu_miso = ad_miso_a;
assign da_mosi = mcu_mosi;
//assign WR_CPLD = ((ARM9200_WR | ARM9200_nCS2)) && (ARM9200_ADDR[11:10] == sw[1:0]);
//assign RD_CPLD = (~(ARM9200_RD | ARM9200_nCS2)) && (ARM9200_ADDR[11:10] == sw[1:0]);
//
//assign RD_DEVID = (~(ARM9200_RD | ARM9200_nCS6)) && (ARM9200_ADDR[11:10] == sw[1:0]);
assign WR_CPLD = ((ARM9200_WR | ARM9200_nCS2)) ;
assign RD_CPLD = (~(ARM9200_RD | ARM9200_nCS2)) ;
assign RD_DEVID = (~(ARM9200_RD | ARM9200_nCS6)) ;
assign ARM9200_DATA[15:0] = RD_CPLD ? RD_DATA[15:0] : 16'hzzzz;
assign ad_rst = ad_rst_r;
assign ad_convsta = ad_convsta_r;
//assign ad_cs_n = ad_en_r ? ad_cs_n_r : 1'b1;
assign ad_cs_n = mcu_npcs1;
assign da_cs_n = da_en_r ? da_cs_n_r : 1'b1;
assign da_rst = da_rst_r;
// MCU读取数据
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
RD_DATA[15:0] <= 16'hzzzz;
else
begin
if(RD_CPLD)
begin
if({ARM9200_ADDR[15:12],ARM9200_ADDR[7:0]} == 12'b101000000000)
RD_DATA[15:0] <= {15'h0,ad_busy};
end
else if(RD_DEVID)
begin
if({ARM9200_ADDR[15:12],ARM9200_ADDR[7:0]} == 12'b111100000000)
begin
RD_DATA[15:0] <= {12'h000,DEVID};
end
else
RD_DATA[15:0] <= 16'hzzzz;
end
else
RD_DATA[15:0] <= 16'hzzzz;
end
end
//MCU写数据
always@( posedge WR_CPLD or negedge rst_n)
begin
if(!rst_n)
begin
ad_rst_r <= 0;
ad_convsta_r <= 1;
ad_rst_r <= 0;
ad_cs_n_r <= 0;
da_cs_n_r <= 0;
da_rst_r <= 1;
ad_en_r <= 0;
da_en_r <= 0;
end
else
begin
case({ARM9200_ADDR[15:12],ARM9200_ADDR[7:0]})
//AD部分
//转换输出
12'b101100010000: ad_convsta_r <= ARM9200_DATA[0];
// //片选
// 12'b101100100000: ad_cs_n_r <= ARM9200_DATA[0];
//复位
12'h101100110000: ad_rst_r <= ARM9200_DATA[0];
//DA部分
// 片选
12'b101101000000: da_cs_n_r <= ARM9200_DATA[0];
//复位
12'b101101010000: da_rst_r <= ARM9200_DATA[0];
// // AD使能
// 12'b101101100000: ad_en_r <= ARM9200_DATA[0];
// DA使能
12'b101101110000: da_en_r <= ARM9200_DATA[0];
// default: ;
endcase
end
end
endmodule
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