cy7c68013 slavefifo 通信失败求助

只看该作者 · 2013-3-3 10:29

本帖最后由飘髯水巾于 2013-3-3 15:00 编辑

小弟是一个新手，刚刚接触CY7c68013，遇到了这样一个问题。
我想做一个数据采集卡。现在想做一个简单的验证，FPGA控制CY7c68013 slavefifo。采用auto in同步传输16位数据到上位机，FPGA用PLL产生IFCLK为15MHZ,addr0和addr1都为高电平，选择端点8，FPGA产生一组自增的数据，与CY7c68013的FD0到FD15相连。所有引脚设置为低有效，当CY7C68013缓冲区没满时，则flagb为高电平，fpga检测这个高电平，则将slwr拉低。也就是，fpga一直产生数据，cy7c68013一直把这组自增的数据传给上位机。固件程序我没做任何修改，只把TD_Init做了修改，如下：
void TD_Init(void)          // Called once at startup
{
IFCONFIG=0x03; // use IFCLK pin driven by external logic (5MHz to 48MHz)
               // use slave FIFO interface pins driven sync by external master
SYNCDELAY;

REVCTL=0x01; // REVCTL.0 and REVCTL.1 set to 0
SYNCDELAY;

EP6CFG=0x00;
SYNCDELAY;    // sets EP8 valid for IN,4 buffers,512byte,in,
EP2CFG=0x00;
SYNCDELAY; // other endpoints are invalid
EP4CFG=0x00;
SYNCDELAY;
EP8CFG=0xE2;
SYNCDELAY;

FIFORESET=0x80;  //reset all FIFOS
SYNCDELAY;
FIFORESET=0x02;
SYNCDELAY;
FIFORESET=0x04;
SYNCDELAY;
FIFORESET=0x06;
SYNCDELAY;
FIFORESET=0x08;
SYNCDELAY;
FIFORESET=0x00;
SYNCDELAY;
EP8FIFOCFG = 0x0D;  // lets the EZ-USB auto commit IN packet
SYNCDELAY;       // gives the ability to send zero length packets
                  // sets the slave FIFO interface to 16-bit
PINFLAGSAB=0x00;  // defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0]
SYNCDELAY;    // FLAGB as full flag, as pointed to by FIFOADR[1:0]
PINFLAGSCD=0x00;  // FLAGC as empty flag, as pointed to by FIFOADR[1:0]
SYNCDELAY;    // won't generally need FLAGD
PORTACFG = 0x00;
SYNCDELAY;
FIFOPINPOLAR=0x00; // set all slave FIFO interface pins as active low
SYNCDELAY;

EP8AUTOINLENH = 0x02;
SYNCDELAY;
EP8AUTOINLENL = 0x00;
SYNCDELAY;
EP8FIFOPFH=0x80;
SYNCDELAY;
EP8FIFOPFL=0x00;
SYNCDELAY;
}

------------------------------------------------------------------
可是通过USB console 下载程序以后，点击 bulk trans要么trans failed  要么只能出现几个看似不太对的数据就不传输了。上图。求大神指导我一下，跪求了...我现在是用的开发板，如果验证可以的话，自己会画画板。现在卡在这了好痛苦。。。