#include<pic.h>
__CONFIG(0X3B31);
#define _nop_() asm("nop")
#define SCK RD0
#define MISO RD1
#define MOSI RD2
#define CSN RD3
#define GDO0 RD4
#define GDO2 RD5
#define WRITE_BURST 0x40 //连续写入
#define READ_SINGLE 0x80 //读
#define READ_BURST 0xC0 //连续读
#define BYTES_IN_RXFIFO 0x7F //接收缓冲区的有效字节数
#define CRC_OK 0x80 //CRC校验通过位标志
#define INT8U unsigned char
#define INT16U unsigned int
// CC2500/CC1100 STROBE, CONTROL AND STATUS REGSITER
#define CCxxx0_IOCFG2 0x00 // GDO2 output pin configuration
#define CCxxx0_IOCFG1 0x01 // GDO1 output pin configuration
#define CCxxx0_IOCFG0 0x02 // GDO0 output pin configuration
#define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
#define CCxxx0_SYNC1 0x04 // Sync word, high INT8U
#define CCxxx0_SYNC0 0x05 // Sync word, low INT8U
#define CCxxx0_PKTLEN 0x06 // Packet length
#define CCxxx0_PKTCTRL1 0x07 // Packet automation control
#define CCxxx0_PKTCTRL0 0x08 // Packet automation control
#define CCxxx0_ADDR 0x09 // Device address
#define CCxxx0_CHANNR 0x0A // Channel number
#define CCxxx0_FSCTRL1 0x0B // Frequency synthesizer control
#define CCxxx0_FSCTRL0 0x0C // Frequency synthesizer control
#define CCxxx0_FREQ2 0x0D // Frequency control word, high INT8U
#define CCxxx0_FREQ1 0x0E // Frequency control word, middle INT8U
#define CCxxx0_FREQ0 0x0F // Frequency control word, low INT8U
#define CCxxx0_MDMCFG4 0x10 // Modem configuration
#define CCxxx0_MDMCFG3 0x11 // Modem configuration
#define CCxxx0_MDMCFG2 0x12 // Modem configuration
#define CCxxx0_MDMCFG1 0x13 // Modem configuration
#define CCxxx0_MDMCFG0 0x14 // Modem configuration
#define CCxxx0_DEVIATN 0x15 // Modem deviation setting
#define CCxxx0_MCSM2 0x16 // Main Radio Control State Machine configuration
#define CCxxx0_MCSM1 0x17 // Main Radio Control State Machine configuration
#define CCxxx0_MCSM0 0x18 // Main Radio Control State Machine configuration
#define CCxxx0_FOCCFG 0x19 // Frequency Offset Compensation configuration
#define CCxxx0_BSCFG 0x1A // Bit Synchronization configuration
#define CCxxx0_AGCCTRL2 0x1B // AGC control
#define CCxxx0_AGCCTRL1 0x1C // AGC control
#define CCxxx0_AGCCTRL0 0x1D // AGC control
#define CCxxx0_WOREVT1 0x1E // High INT8U Event 0 timeout
#define CCxxx0_WOREVT0 0x1F // Low INT8U Event 0 timeout
#define CCxxx0_WORCTRL 0x20 // Wake On Radio control
#define CCxxx0_FREND1 0x21 // Front end RX configuration
#define CCxxx0_FREND0 0x22 // Front end TX configuration
#define CCxxx0_FSCAL3 0x23 // Frequency synthesizer calibration
#define CCxxx0_FSCAL2 0x24 // Frequency synthesizer calibration
#define CCxxx0_FSCAL1 0x25 // Frequency synthesizer calibration
#define CCxxx0_FSCAL0 0x26 // Frequency synthesizer calibration
#define CCxxx0_RCCTRL1 0x27 // RC oscillator configuration
#define CCxxx0_RCCTRL0 0x28 // RC oscillator configuration
#define CCxxx0_FSTEST 0x29 // Frequency synthesizer calibration control
#define CCxxx0_PTEST 0x2A // Production test
#define CCxxx0_AGCTEST 0x2B // AGC test
#define CCxxx0_TEST2 0x2C // Various test settings
#define CCxxx0_TEST1 0x2D // Various test settings
#define CCxxx0_TEST0 0x2E // Various test settings
// Strobe commands
#define CCxxx0_SRES 0x30 // Reset chip.
#define CCxxx0_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
// If in RX/TX: Go to a wait state where only the synthesizer is
// running (for quick RX / TX turnaround).
#define CCxxx0_SXOFF 0x32 // Turn off crystal oscillator.
#define CCxxx0_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
// (enables quick start).
#define CCxxx0_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
// MCSM0.FS_AUTOCAL=1.
#define CCxxx0_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
// MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled:
// Only go to TX if channel is clear.
#define CCxxx0_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
// Wake-On-Radio mode if applicable.
#define CCxxx0_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
#define CCxxx0_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
#define CCxxx0_SPWD 0x39 // Enter power down mode when CSn goes high.
#define CCxxx0_SFRX 0x3A // Flush the RX FIFO buffer.
#define CCxxx0_SFTX 0x3B // Flush the TX FIFO buffer.
#define CCxxx0_SWORRST 0x3C // Reset real time clock.
#define CCxxx0_SNOP 0x3D // No operation. May be used to pad strobe commands to two
// INT8Us for simpler software.
#define CCxxx0_PARTNUM 0x30
#define CCxxx0_VERSION 0x31
#define CCxxx0_FREQEST 0x32
#define CCxxx0_LQI 0x33
#define CCxxx0_RSSI 0x34
#define CCxxx0_MARCSTATE 0x35
#define CCxxx0_WORTIME1 0x36
#define CCxxx0_WORTIME0 0x37
#define CCxxx0_PKTSTATUS 0x38
#define CCxxx0_VCO_VC_DAC 0x39
#define CCxxx0_TXBYTES 0x3A
#define CCxxx0_RXBYTES 0x3B
#define CCxxx0_PATABLE 0x3E
#define CCxxx0_TXFIFO 0x3F
#define CCxxx0_RXFIFO 0x3F
//-------------------------------------------------------------------------------------------------------
// RF_SETTINGS is a data structure which contains all relevant CCxxx0 registers
typedef struct S_RF_SETTINGS{
INT8U FSCTRL2; //自已加的
INT8U FSCTRL1; // Frequency synthesizer control.
INT8U FSCTRL0; // Frequency synthesizer control.
INT8U FREQ2; // Frequency control word, high INT8U.
INT8U FREQ1; // Frequency control word, middle INT8U.
INT8U FREQ0; // Frequency control word, low INT8U.
INT8U MDMCFG4; // Modem configuration.
INT8U MDMCFG3; // Modem configuration.
INT8U MDMCFG2; // Modem configuration.
INT8U MDMCFG1; // Modem configuration.
INT8U MDMCFG0; // Modem configuration.
INT8U CHANNR; // Channel number.
INT8U DEVIATN; // Modem deviation setting (when FSK modulation is enabled).
INT8U FREND1; // Front end RX configuration.
INT8U FREND0; // Front end RX configuration.
INT8U MCSM0; // Main Radio Control State Machine configuration.
INT8U FOCCFG; // Frequency Offset Compensation Configuration.
INT8U BSCFG; // Bit synchronization Configuration.
INT8U AGCCTRL2; // AGC control.
INT8U AGCCTRL1; // AGC control.
INT8U AGCCTRL0; // AGC control.
INT8U FSCAL3; // Frequency synthesizer calibration.
INT8U FSCAL2; // Frequency synthesizer calibration.
INT8U FSCAL1; // Frequency synthesizer calibration.
INT8U FSCAL0; // Frequency synthesizer calibration.
INT8U FSTEST; // Frequency synthesizer calibration control
INT8U TEST2; // Various test settings.
INT8U TEST1; // Various test settings.
INT8U TEST0; // Various test settings.
INT8U IOCFG2; // GDO2 output pin configuration
INT8U IOCFG0; // GDO0 output pin configuration
INT8U PKTCTRL1; // Packet automation control.
INT8U PKTCTRL0; // Packet automation control.
INT8U ADDR; // Device address.
INT8U PKTLEN; // Packet length.
} RF_SETTINGS;
static void delay(unsigned int s)
{
unsigned int i;
for(i=0; i<s; i++);
for(i=0; i<s; i++);
}
void halWait(INT16U timeout) {
do {
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
} while (--timeout);
}
INT8U SpiTxRxByte(INT8U dat)
{
INT8U i,temp;
temp=0;
SCK = 0;
for(i=0; i<8; i++)
{
if(dat & 0x80)
{
MOSI = 1;
}
else MOSI = 0;
dat <<= 1;
SCK = 1;
_nop_();
_nop_();
temp <<= 1;
if(MISO)temp++;
SCK = 0;
_nop_();
_nop_();
}
return temp;
}
INT8U halSpiReadReg(INT8U addr)
{
INT8U temp,value;
temp=addr|READ_SINGLE;
CSN=0;
while(MISO);
SpiTxRxByte(temp);
value=SpiTxRxByte(0);
CSN=1;
return value;
}
void RESET_CC1100(void)
{
CSN = 0;
while (MISO);
SpiTxRxByte(CCxxx0_SRES); //写入复位命令
while (MISO);
CSN = 1;
}
void POWER_UP_RESET_CC1100(void)
{
CSN = 1;
halWait(1);
CSN = 0;
halWait(1);
CSN = 1;
halWait(41);
RESET_CC1100(); //复位CC1100
}
void halSpiWriteReg(INT8U addr,INT8U value)
{
CSN=0;
while(MISO);
SpiTxRxByte(addr);
SpiTxRxByte(value);
CSN=1;
}
void halSpiWriteBurstReg(INT8U addr, INT8U *buffer, INT8U count)
{
INT8U i, temp;
temp = addr | WRITE_BURST;
CSN = 0;
while (MISO);
SpiTxRxByte(temp);
for (i = 0; i < count; i++)
{
SpiTxRxByte(buffer[i]);
}
CSN = 1;
}
//*****************************************************************************************
//函数名：void halSpiStrobe(INT8U strobe)
//输入：命令
//输出：无
//功能描述：SPI写命令
//*****************************************************************************************
void halSpiStrobe(INT8U strobe)
{
CSN = 0;
while (MISO);
SpiTxRxByte(strobe); //写入命令
CSN = 1;
}
void halSpiReadBurstReg(INT8U addr, INT8U *buffer, INT8U count)
{
INT8U i,temp;
temp = addr | READ_BURST; //写入要读的配置寄存器地址和读命令
CSN = 0;
while (MISO);
SpiTxRxByte(temp);
for (i = 0; i < count; i++)
{
buffer[i] = SpiTxRxByte(0);
}
CSN = 1;
}
INT8U halSpiReadStatus(INT8U addr)
{
INT8U value,temp;
temp = addr | READ_BURST; //写入要读的状态寄存器的地址同时写入读命令
CSN = 0;
while (MISO);
SpiTxRxByte(temp);
value = SpiTxRxByte(0);
CSN = 1;
return value;
}
const RF_SETTINGS rfSettings = {
0x00,
0x0b, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x10, // FREQ2 Frequency control word, high byte.
0xA7, // FREQ1 Frequency control word, middle byte.
0x62, // FREQ0 Frequency control word, low byte.
0xcd, // MDMCFG4 Modem configuration.
0x3b, // MDMCFG3 Modem configuration.
0x73, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x15, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xb6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end RX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x1d, // FOCCFG Frequency Offset Compensation Configuration.
0x1c, // BSCFG Bit synchronization Configuration.
0xc7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xb2, // AGCCTRL0 AGC control.
0xEa, // FSCAL3 Frequency synthesizer calibration.
0x0A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x11, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x88, // TEST2 Various test settings.
0x31, // TEST1 Various test settings.
0x0B, // TEST0 Various test settings.
0x0B, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
0x05, // PKTCTRL1 Packet automation control. //地址检测
0x00, // ADDR Device address.
0x0c // PKTLEN Packet length.
};
INT8U PaTabel[8]={0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60};
void halRfWriteRfSettings(void)
{
halSpiWriteReg(CCxxx0_FSCTRL0, rfSettings.FSCTRL2);//自已加的
// Write register settings
halSpiWriteReg(CCxxx0_FSCTRL1, rfSettings.FSCTRL1);
halSpiWriteReg(CCxxx0_FSCTRL0, rfSettings.FSCTRL0);
halSpiWriteReg(CCxxx0_FREQ2, rfSettings.FREQ2);
halSpiWriteReg(CCxxx0_FREQ1, rfSettings.FREQ1);
halSpiWriteReg(CCxxx0_FREQ0, rfSettings.FREQ0);
halSpiWriteReg(CCxxx0_MDMCFG4, rfSettings.MDMCFG4);
halSpiWriteReg(CCxxx0_MDMCFG3, rfSettings.MDMCFG3);
halSpiWriteReg(CCxxx0_MDMCFG2, rfSettings.MDMCFG2);
halSpiWriteReg(CCxxx0_MDMCFG1, rfSettings.MDMCFG1);
halSpiWriteReg(CCxxx0_MDMCFG0, rfSettings.MDMCFG0);
halSpiWriteReg(CCxxx0_CHANNR, rfSettings.CHANNR);
halSpiWriteReg(CCxxx0_DEVIATN, rfSettings.DEVIATN);
halSpiWriteReg(CCxxx0_FREND1, rfSettings.FREND1);
halSpiWriteReg(CCxxx0_FREND0, rfSettings.FREND0);
halSpiWriteReg(CCxxx0_MCSM0 , rfSettings.MCSM0 );
halSpiWriteReg(CCxxx0_FOCCFG, rfSettings.FOCCFG);
halSpiWriteReg(CCxxx0_BSCFG, rfSettings.BSCFG);
halSpiWriteReg(CCxxx0_AGCCTRL2, rfSettings.AGCCTRL2);
halSpiWriteReg(CCxxx0_AGCCTRL1, rfSettings.AGCCTRL1);
halSpiWriteReg(CCxxx0_AGCCTRL0, rfSettings.AGCCTRL0);
halSpiWriteReg(CCxxx0_FSCAL3, rfSettings.FSCAL3);
halSpiWriteReg(CCxxx0_FSCAL2, rfSettings.FSCAL2);
halSpiWriteReg(CCxxx0_FSCAL1, rfSettings.FSCAL1);
halSpiWriteReg(CCxxx0_FSCAL0, rfSettings.FSCAL0);
halSpiWriteReg(CCxxx0_FSTEST, rfSettings.FSTEST);
halSpiWriteReg(CCxxx0_TEST2, rfSettings.TEST2);
halSpiWriteReg(CCxxx0_TEST1, rfSettings.TEST1);
halSpiWriteReg(CCxxx0_TEST0, rfSettings.TEST0);
halSpiWriteReg(CCxxx0_IOCFG2, rfSettings.IOCFG2);
halSpiWriteReg(CCxxx0_IOCFG0, rfSettings.IOCFG0);
halSpiWriteReg(CCxxx0_PKTCTRL1, rfSettings.PKTCTRL1);
halSpiWriteReg(CCxxx0_PKTCTRL0, rfSettings.PKTCTRL0);
halSpiWriteReg(CCxxx0_ADDR, rfSettings.ADDR);
halSpiWriteReg(CCxxx0_PKTLEN, rfSettings.PKTLEN);
}
/*void halRfSendPacket(INT8U *txBuffer,INT8U size)
{
halSpiWriteReg(CCxxx0_TXFIFO,size);
halSpiWriteBurstReg(CCxxx0_TXFIFO,txBuffer,size);
halSpiStrobe(CCxxx0_SFTX);
// while(!GDO0);
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
while(GDO0);
halSpiStrobe(CCxxx0_SFTX);
}*/
INT8U halRfReceivePacket(INT8U *rxBuffer,INT8U *length)
{
INT8U status[2];
INT8U packetLength;
halSpiStrobe(CCxxx0_SRX);
while(GDO0);
if ((halSpiReadStatus(CCxxx0_RXBYTES) & BYTES_IN_RXFIFO)) //如果接的字节数不为0
{
packetLength = halSpiReadReg(CCxxx0_RXFIFO);//读出第一个字节，此字节为该帧数据长度
if (packetLength <= *length) //如果所要的有效数据长度小于等于接收到的数据包的长度
{
halSpiReadBurstReg(CCxxx0_RXFIFO, rxBuffer, packetLength); //读出所有接收到的数据
*length = packetLength; //把接收数据长度的修改为当前数据的长度
// Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
halSpiReadBurstReg(CCxxx0_RXFIFO, status, 2); //读出CRC校验位
halSpiStrobe(CCxxx0_SFRX); //清洗接收缓冲区
return (status[1] & CRC_OK); //如果校验成功返回接收成功
}
else
{
*length = packetLength;
halSpiStrobe(CCxxx0_SFRX); //清洗接收缓冲区
return 0;
}
}
else
return 0;
}
void SpiInit(void)
{
CSN=0;
SCK=0;
CSN=1;
TRISD=0X32;
TRISB=0;
PORTB=0XFF;
PORTD=0X00;
}
/*****************************************************************************************
//函数名：CpuInit()
//输入：无
//输出：无
//功能描述：SPI初始化程序
/*****************************************************************************************/
void CpuInit(void)
{
SpiInit();
delay(5000);
}
void main()
{
INT8U temp;
// INT8U TxBuf[8]={"0110011"}; // 8字节, 如果需要更长的数据包,请正确设置
INT8U RxBuf[8]={"0110100"};
temp=8;
CpuInit();
POWER_UP_RESET_CC1100();
halRfWriteRfSettings();
halSpiWriteBurstReg(CCxxx0_PATABLE, PaTabel, 8);
while(1)
{
halRfReceivePacket(RxBuf,&temp);
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
RB0=RxBuf[0];RB1=RxBuf[1];RB2=RxBuf[2];RB3=RxBuf[3];RB4=RxBuf[4];
}
} |
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