PhysDesignRules:1860 - The delay controller
Radio420x_l/limeDAC_l/IDELAYCTRL_inst is placed at site IDELAYCTRL_X0Y4 but
none of the IODELAYs calibrated by this IDELAYCTRL are being used. The
IDELAYCTRL should be removed from the design and the <idelayctrl_site.rdy>
net should be connected to GLOBAL_LOGIC_1. A script is available to automate
this process. For more details, please search the Xilinx Answers Database for
IDELAYCTRL. 有没有大神知道这该怎么改的？谢谢了！ |
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