Verilog问题

只看该作者 · 2013-3-26 19:24

module test(led1,led2,led3,led4);

output led1,led2,led3,led4;

integer i;

for(i=1;i<20;i=i+1)
  begin
assign led1 = 1;
assign led2 = 1;
assign led3 = 1;
assign led4 = 1;
  end

endmodule

然后报错：
Error (10170): Verilog HDL syntax error at test.v(8) near text "for";  expecting an identifier ("for" is a reserved keyword ), or "endmodule", or a parallel statement
Error (10170): Verilog HDL syntax error at test.v(14) near text "end";  expecting an identifier ("end" is a reserved keyword ), or "endmodule", or a parallel statement
Error (10112): Ignored design unit "test" at test.v(1) due to previous errors
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
Error: Peak virtual memory: 199 megabytes
Error: Processing ended: Thu Jan 17 17:36:19 2013
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 5 errors, 0 warnings

只看该作者 · 2013-3-26 19:39

不明白你是要做时序电路还是结合电路。

1万 · 2013-3-26 19:50

你的代码感觉非常奇怪。
for(i=1;i<20;i=i+1)
begin
assign led1 = 1;
assign led2 = 1;
assign led3 = 1;
assign led4 = 1;
end

为什么对一个端口连续操作相同的19次操作。

只看该作者 · 2013-3-26 20:03

把两种语言学一起去了？

Verilog问题

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