- `timescale 1ns/1ps
- module ADTest();
-
- reg clk,rst;
- wire [15:0] ARM9200_Data;
- reg Data_En;
- reg [15:0] ARM9200_Data_r;
- reg [15:0] ARM9200_Addr;
- reg ARM_WR,ARM_RD;
- reg ARM_nCS2,ARM_nCS6;
- wire [1:0] sw;
- assign sw[1:0] = 0;
- assign ARM9200_Data = Data_En ? ARM9200_Data_r : 16'hzzzz;
- initial
- begin
-
- clk = 0;
- rst = 0;
- #10
- rst = 1;
- end
- initial
- begin
- ARM_nCS2 = 1;
- ARM_WR = 1;
- ARM_RD =1;
- Data_En = 0;
- ARM_nCS6 = 1;
-
- #100
- ARM9200_Addr[15:0] = 16'b1011000000000010;
- Data_En = 1;
- ARM9200_Data_r = 1;
- #100
- ARM_nCS2 = 0;
- ARM_WR = 0;
- #100
- ARM_nCS2 = 1;
- ARM_WR = 1;
-
- end
- always
- begin
- #10 clk = ~clk;
- end
-
- RDC_AD_V21 RDC_AD_V21_test(.sys_clk(clk),.rst_n(rst),.ARM9200_WR(RM_WR),.ARM9200_RD(ARM_RD),.ARM9200_nCS2(RM_nCS2),.ARM9200_nCS6(ARM_nCS6),.ARM9200_DATA(ARM9200_Data),
- .ARM9200_ADDR(ARM9200_Addr[15:0]),.sw(sw),.ad_rst(),.ad_sclk(),.ad_miso_a(),.ad_miso_b(),.ad_busy(),.ad_cs_n(),.ad_convsta(),.da_rst(),.da_mosi(),.da_sclk(),.da_cs_n());
-
-
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