请搞过PCI9054的朋友进来看看

只看该作者 · 2013-4-22 16:56

最近在看PCI这块，用的是PCI9054+FPGA  的例程，有段代码看的有问题：与手册上给的时序匹配不起来(BLAST 和 ADS信号)：把代码贴出来
这段代码是实现了上位机控制4个LED的例子，地址是14‘b1 的时候读入主机发过来的数据线上的数据，判断哪个灯亮。用的应该是C模式 : PCI target Single Write
module WITH_PCI_LED_RUN(
   clkin,
   lrst,ld,ads,lwr,ready,blast,lhold,lholda,la,ccs,bterm,
   led
   );

input clkin;
input lrst,ads,lwr,blast,lhold;
input [13:0] la;
output ready,lholda,ccs,bterm;
input [31:0] ld;
output  [3:0]  led;

reg  [3:0]  led;
reg  [24:0] count;
reg  [1:0]  state;
wire clk;
reg lholda;
wire ready,ccs,bterm;

reg readyflag;
reg  [7:0] LEDByControl;
//--计数分频-------------------------------------
always @ (posedge clkin)
count <= count+1;
assign clk = count[24];
//--LED控制--------------------------------
always @ (posedge clk)
begin
  case(LEDByControl)
8'd1: led <= 4'b0001;
8'd2: led <= 4'b0010;
8'd3: led <= 4'b0100;
8'd4: led <= 4'b1000;
8'd5: case(state)
   2'b00: led <= 4'b0001;
   2'b01: led <= 4'b0010;
   2'b10: led <= 4'b0100;
   2'b11: led <= 4'b1000;
   endcase
default:led <= 4'b0000;
  endcase
end

always @ (posedge clk)
state <= state+1;

//--PCI本地控制器-------------------------------
always @(posedge clkin)
lholda <= lhold;

always @(posedge clkin or negedge lrst)
begin
  if(!lrst)
begin
readyflag <= 1'b0;
LEDByControl[7:0] <= 8'b0;
end
  else if(!ads & lwr & blast & la[13:0] == 14'b1)
begin
readyflag <= 1'b1;
end
  else if(ads & lwr & blast & readyflag == 1'b1 & la[13:0] == 14'b1)
begin
readyflag <= 1'b1;
end
  else if(ads & lwr & !blast & readyflag == 1'b1 & la[13:0] == 14'b1)
begin
LEDByControl[7:0] <= ld[31:24];
readyflag <= 1'b0;
end
  else
begin
LEDByControl[7:0] <= LEDByControl[7:0];
readyflag <= 1'b0;
end
end
//-----------------------------------------------------
assign ccs = 1'b1;
assign bterm = 1'b1;
assign ready = 1'b0;

endmodule