贴出一段Verilog的程序，请教~

只看该作者 · 2013-5-6 21:43

困扰了我很久很久的问题：快哭了。。。。
很简单的程序如下：以一个状态机用于控制进程，第二段用于端口写数据和命令，第三段控制LED灯指示，成功则led亮、led2灭；否则led灭、led2亮。现在为什么下载成功以后两盏led灯不停闪烁呢？？
reg[7:0] reg_int=0;
reg[7:0] data_372;
reg a0,wr,rd,cs,led_en,led2_en,t1;
reg[3:0] state;
reg[5:0] i,j,k;

parameter idle=0,wr_cmd_start=1,wr_wait=2,wr_cmd_end=3,delay=4;
parameter wr_cmd_start2=5,wr_wait2=6,wr_cmd_end2=7,wr_data_start=8,data_wait=9,wr_data_end=10,delay2=11,rd_data_start2=12,rd_wait2=13,rd_data_end2=14;

always@(posedge clk_1mhz or posedge rst or posedge sw)
if(sw==1)
      state<=idle;
   else
begin
   case(state)
         idle:
   begin
   cs<=0;i<=0;j<=0;k<=0;
   rd<=0;
   wr<=0;
   a0<=0;t1<=0;
               if(rst==1) state<=wr_cmd_start;
               else
               state<=idle; end

      wr_cmd_start:  begin
   t1<=1;
   a0<=1;
   rd<=1;
   cs<=0;
   wr<=0;
   state<=wr_wait;end

         wr_wait:
   state<=wr_cmd_end;

      wr_cmd_end: begin
   a0<=1;
   rd<=1;
   cs<=0;
   wr<=0;
   t1<=0;
   state<=delay;end

   delay:
      if (k>=6'b100000&&i>=6'b011001&&j>=6'b011001)
   begin  k<=6'b000000;i<=6'b000000;j<=6'b000000;state<=wr_cmd_start2;end
   else if (j>=5'b011001&&i>=5'b011001)
   begin  i<=6'b000000;j<=6'b000000;k<=k+6'b1;state<=delay;end
   else if (j>=5'b011001)
   begin  j<=6'b000000;i<=i+6'b1;state<=delay;end
   else
   begin  j<=j+6'b1;state<=delay;end    //delay 40ms

wr_cmd_start2: begin //xie ming ling
   a0<=1;
   rd<=1;
   cs<=0;
   wr<=0;
   t1<=0;
   state<=wr_wait2;end

wr_wait2:          //xie deng dai
   state<=wr_cmd_end2;

wr_cmd_end2: begin
   a0<=1;
   rd<=1;
   cs<=0;
   t1<=0;
   wr<=0;state<=wr_data_start;end

wr_data_start: //xie ming ling
begin    a0<=0;
   rd<=1;
   cs<=0;
   wr<=0;

   state<=data_wait;
   end

data_wait:          //xie deng dai
   state<=wr_data_end;

wr_data_end: begin
   a0<=1;
   rd<=1;
   cs<=0;
   wr<=0;state<=delay2;end

rd_data_start2: begin
   a0<=0;
   rd<=0;
   cs<=0;
   wr<=1;
   state<=delay2;end

      delay2:
      if (reg_int==8'h51) state<=rd_data_end2;
      else  if (k>=6'b110100)
   begin             k<=6'b000000;state<=idle;end
   else
   begin  k<=k+6'b1;state<=delay2;end    //delay 20us




rd_data_end2:
               begin a0<=0;rd<=0;cs<=0;wr<=1;
   state<=rd_data_end2; end
   default:state<=idle;
endcase
end

always@(posedge clk_1mhz)
begin
if (cs==0&&wr==0&&rd==1&&a0 ==1)
      if (t1==1) data_372<=8'h05;
      else if (t1==0) data_372<=8'h15;
      else  data_372<=8'bzzzzzzzz;
else if (cs==0&&rd==1&&wr==0&&a0==0) data_372<=8'h02;
else if (cs==0&&rd==0&&wr==1) reg_int<=data_372;
else data_372<=8'bzzzzzzzz;
end

always@(posedge clk_1mhz)
   if (reg_int==8'h51) begin led_en<=1;led2_en<=0;end
   else if (reg_int==8'h5f) begin led_en<=0;led2_en<=1;end
   else begin led_en<=1;led2_en<=1;end
endmodule

只看该作者 · 2013-5-7 18:32

always@(posedge clk_1mhz or posedge rst or posedge sw)

只看到上面这一句，下面没细看，问下你这个程序没报错？

只看该作者 · 2013-5-7 22:15

Backkom80 发表于 2013-5-7 18:32
always@(posedge clk_1mhz or posedge rst or posedge sw)

只看到上面这一句，下面没细看，问下你这个程序 ...

没有啊，，，怎么了？

只看该作者 · 2013-5-7 22:45

本帖最后由 resxpl 于 2013-5-7 22:56 编辑

1) rd_data_start2状态没有用到
2) else data_372<=8'bzzzzzzzz; // 没有用处的代码
3) state逻辑太复杂,
其中i, j, k只是简单的延时, 没有必要放到state输入逻辑中, 可以放到另一个always中.