"WARNING: Xst:766 - file_name (Line #). Generating a Black Box for component <component_name>.
官网的解决办法是：
To avoid "black box" warning messages, add the following lines to your HDL code:
VHDL:
architecture <architecture_name>
:
attribute box_type : string;
attribute box_type of <component_name> : component is "black_box";
:
begin
Verilog:
//synthesis attribute box_type <module_name> "black_box"
----------------------------------------------------------------------------------------
我用的Verilog，是加注释还是去掉注释符号？这段语句应该加在哪个文件里呢？
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楼主
