1.现在又一个100M的时钟以0~63分频，需要检测在这个分频区间内的任何一次分频变化。统计并累加频率跳变次数。
代码如下：
module test(
clkin,
clkref,
rst,
frq
);
input clkin,clkref,rst;
output [15:0] frq;
reg [15:0] frq;
//--------------------------div
reg clk_div2;
always@(posedge clkin or negedge rst)
if(!rst)
clk_div2<=0;
else
clk_div2<=~clk_div2;
wire clk_div3/* synthesis keep */;
assign clk_div3=~(~clk_div2);
wire clk_div4/* synthesis keep */;
assign clk_div4=~(~clk_div3);
wire clk_div5/* synthesis keep */;
assign clk_div5=~(~clk_div4);
wire clk_div6/* synthesis keep */;
assign clk_div6=~(~clk_div5);
wire clk_div7/* synthesis keep */;
assign clk_div7=~(~clk_div6);
wire clk_div8/* synthesis keep */;
assign clk_div8=~(~clk_div7);
wire clk4;
assign clk4=((~clk_div2)&&clk_div7)||((~clk_div7)&&clk_div2);
wire clkref,clk0,clk1,clk2;
pll1 u_pll1(
.areset(~rst),
.inclk0(clkref),
.c0(clk0),
.c1(clk1),
.c2(clk2));
wire [7:0] cnt0,cnt1,cnt2;
lpm u_lpm0(
.aclr(clk4),
.clk_en(~clk4),
.clock(clk0),
.q(cnt0));
lpm u_lpm1(
.aclr(clk4),
.clk_en(~clk4),
.clock(clk1),
.q(cnt1));
lpm u_lpm2(
.aclr(clk4),
.clk_en(~clk4),
.clock(clk2),
.q(cnt2));
reg [7:0] temp1,temp2;
always@(posedge clk4 or negedge rst)
if(!rst)
begin
temp1<=0;
temp2<=0;
end
else
begin
temp1<=cnt0;
temp2<=temp1;
end
reg [7:0] temp3,temp4;
always@(posedge clk4 or negedge rst)
if(!rst)
begin
temp3<=0;
temp4<=0;
end
else
begin
temp3<=cnt1;
temp4<=temp3;
end
reg [7:0] temp5,temp6;
always@(posedge clk4 or negedge rst)
if(!rst)
begin
temp5<=0;
temp6<=0;
end
else
begin
temp5<=cnt2;
temp6<=temp5;
end
always@(posedge clk4 or negedge rst)
if(!rst)
frq<=0;
else
if((temp1==0)||(temp2==0)||(temp3==0)||(temp4==0)||(temp5==0)||(temp6==0) )
frq<=frq;
else
if( (temp2>temp1)&&((temp2-temp1)>=3)&& (temp4>temp3)&&((temp4-temp3)>=3)
&& (temp6>temp5)&&((temp6-temp5)>=3) )
frq<=frq+1;
else if( (temp1>temp2)&&((temp1-temp2)>=3)&&(temp3>temp4)&&((temp3-temp4)>=3)
&&(temp5>temp6)&&((temp5-temp6)>=3) )
frq<=frq+1;
else
frq<=frq;
endmodule
有个问题是在实际变化中会统计漏2~4次。。不知道有没有高手看有没有问题？ |
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