组合逻辑和时序逻辑的关系

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damoyeren| 助理工程师

楼主 | 2013-6-27 11:12 | 只看该作者回帖奖励

|倒序浏览 |阅读模式

时序逻辑, TE, ic, ge, ST

1.下边程序是时序逻辑
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY div_6 IS
GENERIC( DWITH : INTEGER := 6);
PORT( clkin : IN STD_LOGIC;
   clkout: OUT STD_LOGIC
);
END ENTITY;

ARCHITECTURE arc_div_6 OF div_6 IS
SIGNAL temp : INTEGER RANGE DWITH-1 DOWNTO 0;
BEGIN
PROCESS(clkin)
BEGIN
IF(clkin'EVENT AND clkin = '1')THEN
IF( temp = 5 )THEN
   temp <= 0;
ELSE
   temp <= temp + 1;
END IF;
END IF;
END PROCESS;

PROCESS(temp)
BEGIN
IF temp < DWITH/2 THEN
clkout <= '0';
end if;
if temp > DWITH/2 THEN
clkout <= '1';
END IF;
END PROCESS;
END ARCHITECTURE;
2.下边程序是组合逻辑
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY div_6 IS
GENERIC( DWITH : INTEGER := 6);
PORT( clkin : IN STD_LOGIC;
   clkout: OUT STD_LOGIC
);
END ENTITY;

ARCHITECTURE arc_div_6 OF div_6 IS
SIGNAL temp : INTEGER RANGE DWITH-1 DOWNTO 0;
BEGIN
PROCESS(clkin)
BEGIN
IF(clkin'EVENT AND clkin = '1')THEN
IF( temp = 5 )THEN
   temp <= 0;
ELSE
   temp <= temp + 1;
END IF;
END IF;
END PROCESS;

PROCESS(temp)
BEGIN
IF temp < DWITH/2 THEN
clkout <= '0';
  elsif;
clkout <= '1';
END IF;
END PROCESS;
END ARCHITECTURE;
上边的程序就一条语句的差别，怎么就能看出是组合逻辑还是时序逻辑？

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