Job Title: DFT Engineer (Junior-At least 2yrs’ DFT experience/Senior-At least 4yrs’ relative experience)
Department: GPU
Location: Shanghai
Job Description/Qualifications:
Responsibilities:
• Responsible for DFT implementation including test mode controllers, Memory BIST/Repair and JTAG based on DFT plan.
• Responsible for scan insertion, ATPG and post silicon validation.
• Responsible for DFT logic and pattern verification.
• Responsible for ATE chip bringup and failure analysis.
Minimum Requirement:
• BSEE required, MSEE preferred.
• 3+ years of experience in DFT/design field
• Strong logic Design and verification background with experience in STA.
• Must possess a strong knowledge of DFT including scan, ATPG, Test Compression, JTAG and BIST.
• Programming in Perl, tcl and C/C++ is a plus
• Good Englisth communication skills
• Self-motivated and good team player
sophiay@nvidia.com |
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