module sys_in(rst,clk,sdi_in,frame_in
);
input rst,clk;
input [19:0] sdi_in ;
output frame_in;
reg [19:0] idata_r0;
reg [19:0] idata_r1;
reg [19:0] idata_r2;
reg [19:0] idata_r3;
reg [19:0] idata_r4;
reg frame_in_r;
reg [10:0] line;
reg [11:0] point;
assign frame_in =frame_in_r;
always @(posedge clk)
begin
idata_r0<= sdi_in;
idata_r1<= idata_r0;
idata_r2<= idata_r1;
idata_r3<= idata_r2;
idata_r4<= idata_r3;
if (rst)
begin
idata_r0<=20'h00000;
idata_r1<=20'h00000;
idata_r2<=20'h00000;
idata_r3<=20'h00000;
idata_r4<=20'h00000;
point <= 12'h000;
line <=11'b00000000000;
end
else
begin
if((idata_r4==20'hfffff)&&(idata_r3==20'h00000)&&(idata_r2==20'h00000)&&(idata_r1[6]==1))
begin
line[10:0]<={sdi_in[5:2],idata_r0[8:2]};
point <= 12'h001;
end
else
point <= point+1;
end
end
always @(posedge clk)
begin
if (rst)
frame_in_r <=0;
else if((line==11'h006) && (point ==2430) )
frame_in_r<=1'b1 ;
else if((line==11'h006)&& (point ==2630) )
frame_in_r<=1'b0 ;
else
frame_in_r<=frame_in_r;
end
endmodule
上面这段代码实现对输入流数据个数的计数 为什么下载板子调试用逻辑分析仪看是下面的情况
E:\1.jpg
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