ARCHITECTURE BEHV OF GATE_SIGNAL IS SIGNAL COUNT: INTEGER RANGE 0 TO 93:=0; SIGNAL RST: STD_LOGIC; BEGIN PROCESS(CLK,X1_X10_X100HZ,X1K_X10K_X100KHZ) BEGIN IF CLK'EVENT AND CLK='1' THEN IF X1_X10_X100HZ='1' THEN IF COUNT=93 THEN COUNT<=0;RST<='0'; ELSE IF COUNT=50 THEN RST<='1'; END IF; END IF; END IF; ELSE IF X1K_X10K_X100KHZ='1' THEN IF COUNT=18 THEN COUNT<=0;RST<='0'; ELSE IF COUNT=9 THEN RST<='1'; END IF; END IF; END IF; END IF; COUNT<=COUNT+1; END PROCESS; RESET<=RST; END BEHV; 编译时出现错误如下: Error (10483): VHDL error at GATE_SIGNAL.vhd(17): can't infer register for signal "COUNT[0]" because signal does not hold its value outside clock edge! 是不是信号不能重复幅值?我想让输出的频率能够选择。 麻烦帮忙看下! 多谢! |