这是一块别人板子上用的一段代码
module MUX8x1(Z,Din,S);
input[7:0] Din;
output Z;
reg z;
input [2:0] S;
wire S0bar,S1bar,S2bar;
wire T0,T1,T2,T3,T4,T5,T6,T7;
and (T0,Din[0],S2bar,S1bar,S0bar),
(T1,Din[1],S2bar,S1bar,S[0]),
(T2,Din[2],S2bar,S[1],S0bar),
(T3,Din[3],S2bar,S[1],S[0]),
(T4,Din[4],S[2],S1bar,S0bar),
(T5,Din[5],S[2],S1bar,S[0]),
(T6,Din[6],S[2],S[1],S0bar),
(T7,Din[7],S[2],S[1],S[0]);
not (S0bar,S[0]),
(S1bar,S[1]),
(S2bar,S[2]);
or (Z,T0,T1,T2,T3,T4,T5,T6,T7);
endmodule
我用quartsII编译出现错误，错误如下：
Error (10663): Verilog HDL Port Connection error at mydisp.v(23): output or inout port "Z" must be connected to a structural net expression
但是用maxplusII就可以通过。
刚接触cpld，请大虾指点 |
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