ERROR:HDLParsers:3340 - Project file "qq_gen.prj" names two source files, D:/ise1/qq/qq.ant and D:/ise1/qq/qq.vhd, that both define the same primary unit, work/qq
Parsing "qq_gen.prj": 0.03
Simulator:176 - Unable to find any precompiled architecture for entity qq in the library work.
这两个问题怎么解决啊。程序我是用VHDL写例程 |
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