写了一个四选一数据选择器，结果在quatus中一编译就出现这样的错误，不知道为什么，请前辈们帮们分析一下，关系到我学习它的信心啊，帮忙！！！
Error (10170): Verilog HDL syntax error at gete4_1.v(5) near text "case"; expecting an identifier ("case" is a reserved keyword ), or "endmodule", or a parallel statement
Error (10112): Ignored design unit "gate4_1" at gete4_1.v(1) due to previous errors
源程序：
module gate4_1 (a,b,c,d,sel,f);
input a,b,c,d;
input [1:0]sel;
output f;
case(sel)
0:f=a;
1:f=b;
2:f=c;
3:f=d;
endcase
endmodule
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