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写了一个四选一数据选择器，结果在quatus中一编译就出现这样的错误，不知道为什么，请前辈们帮们分析一下，关系到我学习它的信心啊，帮忙！！！<br /><br />Error (10170): Verilog HDL syntax error at gete4_1.v(5) near text "case"; expecting an identifier ("case" is a reserved keyword ), or "endmodule", or a parallel statement<br /><br />Error (10112): Ignored design unit "gate4_1" at gete4_1.v(1) due to previous errors<br /><br />源程序：<br />module gate4_1 (a,b,c,d,sel,f);<br />input a,b,c,d;<br />input [1:0]sel;<br />output f;<br />case(sel)<br />0:f=a;<br />1:f=b;<br />2:f=c;<br />3:f=d;<br />endcase<br />endmodule<br /><br /> |
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