entity delay14 is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic
);
end delay14;
architecture vr2 of delay14 is
signal cn : std_logic_vector(10 downto 0) := (others=>'0');
signal flag : std_logic;
begin
p1:process(clk) -- process(clk,d)
begin
if (clk'event and clk='1')then
if(d='1' and cn="00000000000" and flag='0') then
flag <= '1'; -- 结束时，d='1'一直成立，故增加个标志
cn <= "10000000000";
elsif(cn>"00000000000")then
cn <= cn-'1';
else
cn <="00000000000"; flag <= '0';
end if;
end if;
end process p1;
q <='0' when cn="00000000000" else '1';
end vr2;
这个程序怎么 不能实现连续 １０２４ 个高电平后再变低电平？？ |
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