我想利用PLL在一个IO口上输出400MHz的时钟，输入时钟是100MHz，程序编译没有问题，可是输出脚上没有波形。代码如下，请各位帮我看看，是不是我例化PLL有问题？
module pll400(
input clk_100,
input rst,
output clk_400
);
PLL_BASE #(
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(4), // Multiply value for all CLKOUT clock outputs (1-64) 产生400MHz，需要乘4
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of the clock feedback output (0.0-360.0).
.CLKIN_PERIOD(10), // Input clock period in ns to ps resolution (i.e. 33.333 is 30
// MHz). 输入时钟100MHz，对应的就是10
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128) 不需要进行除法
.CLKOUT0_DIVIDE(1),
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT5_PHASE: Output phase relationship for CLKOUT# clock output (-360.0-360.0).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLK_FEEDBACK("CLKFBOUT"), // Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0")
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "EXTERNAL"
.DIVCLK_DIVIDE(1), // Division value for all output clocks (1-52)
.REF_JITTER(0.1), // Reference Clock Jitter in UI (0.000-0.999).
.RESET_ON_LOSS_OF_LOCK("FALSE") // Must be set to FALSE
)
PLL_BASE_inst (
.CLKFBOUT(CLKFBOUT), // 1-bit output: PLL_BASE feedback output
// CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
.CLKOUT0(clk_400_in), //输出400MHz作为sys_clk
.CLKOUT1(CLKOUT1),
.CLKOUT2(CLKOUT2),
.CLKOUT3(CLKOUT3),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.LOCKED(LOCKED), // 1-bit output: PLL_BASE lock status output
.CLKFBIN(CLKFBOUT), // 1-bit input: Feedback clock input
.CLKIN(clk_100), // 1-bit input: Clock input 100MHz作为输入时钟
.RST(rst) // 1-bit input: Reset input reset输入
);
// End of PLL_BASE_inst instantiation
BUFG BUFG_CLK1 (
.O(clk_400_out), // 1-bit output: Clock buffer output
.I(clk_400_in) // 1-bit input: Clock buffer input
);
ODDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst (
.Q(clk_400), // 1-bit DDR output data
.C0(clk_400_out), // 1-bit clock input
.C1(~clk_400_out), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
endmodule
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