下面这个程序,搞了一个星期了,弄不定啊,用过许多方法。 功能主要在always区里, 当fir_start来时,说明一个周期的开始。之后,会接着有fir_done的脉冲,每个脉冲来后,wraddress的值加一。 可是下明的程序,仿真看,地址就是不加。 请高手,帮忙看看!
module fir_output_buffer( clk, fir_data, fir_done, fir_enable, fir_start, rdaddress321, rdclock, wrclock, q, rst); input [19:0] fir_data; input fir_done,fir_start,clk,rst; output fir_enable; input [3:0] rdaddress321; input rdclock; output [19:0] q; output wrclock; wire [4:0] rdaddress; reg rdaddress4; reg fir_enable; reg wrclock; reg wren; wire [19:0] fir_data; reg [4:0] wraddress; assign rdaddress={rdaddress4,rdaddress321}; tx_ram txram1(fir_data,rdaddress,rdclock,wraddress,wrclock,1,q); reg fir_start_pre,fir_done_pre; always @(posedge clk) begin fir_start_pre<=fir_start; fir_done_pre<=fir_done; if(rst) currentstate<=0; if(fir_start!=fir_start_pre&&fir_start) begin wraddress<=0; end if(fir_done!=fir_done_pre&&fir_done) begin wrclock<=1; wraddress<=wraddress+1; end if(wrclock) wrclock<=0; end endmodule
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