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library ieee;<br />use ieee.std_logic_1164.all; <br />--*************************--<br />ENTITY gat IS<br /> generic(l_time:time; s_time:time);<br />PORT(<br /> b1,b2,b3 : inout bit);--? inout与buffer的区别<br />END gat ; <br />--************************************<br />ARCHITECTURE func OF gat IS<br />BEGIN<br /> signal a1: bit; <br />begin<br /> blk1:block<br /> generic(gb1,gb2:time);<br /> generic map(gb1=>l_time,gb2=>s_time);--？什么意思<br /> PORT (gb1:in bit;gb2:inout bit);--?什么意思<br /> PORT map(gb1=>b1, gb2=>a1);--？什么意思<br /> constant delay:time:=1 ms;<br /> signal s1:bit;--？信号可以在这里定义。。。<br /> begin<br /> s1<=gb1 after delay;<br /> gb2<=s1 after gb1,b1 after gb2;--？这种after到底是等多久<br /> end block blk1;<br /> end func;
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