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module PWM(clk,clk_out,pwm_data,wr);<br />input clk,wr;<br />input[7:0] pwm_data; <br />output clk_out;<br />reg[7:0] reg_data;<br />reg[7:0] counter;<br /><br />always@(posedge wr)<br />begin<br />reg_data<=pwm_data;<br />end<br />always@(posedge clk) <br />begin<br />counter<=counter+1; <br />end<br />assign clk_out=counter>reg_data?0:1;<br />endmodule<br />不知道有没有错误，这也是我刚刚开始写verilog程序,<br />谢谢指点！ |
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楼主
