module PWM(clk,clk_out,pwm_data,wr);
input clk,wr;
input[7:0] pwm_data;
output clk_out;
reg[7:0] reg_data;
reg[7:0] counter;
always@(posedge wr)
begin
reg_data<=pwm_data;
end
always@(posedge clk)
begin
counter<=counter+1;
end
assign clk_out=counter>reg_data?0:1;
endmodule
不知道有没有错误，这也是我刚刚开始写verilog程序,
谢谢指点！ |
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