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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock is
Port ( N : out std_logic_vector(7 downto 0);
P : out std_logic_vector(3 downto 0);
clk : in std_logic;
reset,mode,inc: in std_logic);
end clock;
architecture Behavioral of clock is
SIGNAL divcounter,divcounter1: std_logic_vector(27 downto 0);
SIGNAL divclk,clk2:std_logic;
SIGNAL blink: std_logic_vector(3 downto 0);
SIGNAL scan:std_logic_vector(8 downto 0);
SIGNAL scan_clk:std_logic_vector(1 downto 0);
signal state:std_logic_vector(2 downto 0); --clock state.
SIGNAL sec_counter1,sec_counter2,min_counter1,min_counter2:std_logic_vector(3 downto 0);
--SIGNAL sec_counter1,sec_counter2,min_counter1,min_counter2:std_logic_vector(3 downto 0);
signal data:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clk='1' and clk'event then
if(divcounter>=X"1312D00") then
divcounter<=X"0000000";
divclk<=not divclk;
else
divcounter<=divcounter+'1';
end if;
end if;
end process;
--2Hz
process(clk)
begin
if clk='1' and clk'event then
if(divcounter1>=X"989680") then
divcounter1<=X"0000000";
clk2<=not clk2;
else
divcounter1<=divcounter1+'1';
end if;
end if;
end process;
-- mode change
process(reset,divclk)
begin
if(reset='0') then
state<="000";
elsif(divclk'event and divclk='1') then
if(mode='0') then
if(state>="100") then
state<="000";
else state<=state+'1';
end if;
end if;
end if;
end process;
process(state)
begin
case state is
when "000"=> blink<=(others=>'1');
when "001"=> blink<=(0=>clk2,others=>'0');
when "010"=> blink<=(1=>clk2,others=>'0');
when "011"=> blink<=(2=>clk2,others=>'0');
when "100"=> blink<=(3=>clk2,others=>'0');
when others=>
end case;
end process;
--count
process(divclk,reset,state)
--variable sec_counter1,sec_counter2,min_counter1,min_counter2:std_logic_vector(3 downto 0);
begin
if(reset='0') then
sec_counter1<=(others=>'0');
sec_counter2<=(others=>'0');
min_counter1<=(others=>'0');
min_counter2<=(others=>'0');
elsif (divclk'event and divclk='1') then
case state is
when "000"=>
if(sec_counter1>=X"9") then
sec_counter1<=X"0";
if(sec_counter2>=X"5")then
sec_counter2<=X"0";
if(min_counter1>=X"9")then
min_counter1<=X"0";
if(min_counter2>=X"5")then
min_counter2<=X"0";
else
min_counter2<=min_counter2+'1';
end if;
else
min_counter1<=min_counter1+'1';
end if;
else
sec_counter2<=sec_counter2+'1';
end if;
else
sec_counter1<=sec_counter1+'1';
end if;
when"001"=>
if(inc='0') then
if(min_counter2>=X"5")then
min_counter2<=X"0";
else min_counter2<=min_counter2+'1';
end if;
end if;
when"010"=>
if(inc='0') then
if(min_counter1>=X"9")then
min_counter1<=X"0";
else min_counter1<=min_counter1+'1';
end if;
end if;
when"011"=>
if(inc='0') then
if(sec_counter2>=X"5")then
sec_counter2<=X"0";
else sec_counter2<=sec_counter2+'1';
end if;
end if;
when"100"=>
if(inc='0') then
if(sec_counter1>=X"9")then
sec_counter1<=X"0";
else sec_counter1<=sec_counter1+'1';
end if;
end if;
when others=>
end case;
end if;
end process;
--scan count
process(clk)
begin
if (clk'event and clk='1') then
scan<=scan+1;
end if;
end process;
scan_clk<=scan(8 downto 7);
process(scan_clk)
begin
case scan_clk is
when "00"=>
data<=sec_counter1;
P<="1000" and blink;
when "01"=>
data<=sec_counter2;
P<="0100" and blink;
when "10"=>
data<=min_counter1;
P<="0010" and blink;
when "11"=>
data<=min_counter2;
P<="0001" and blink;
when others=>data<="1111";P<="0000";
end case;
end process;
process(data)
begin
case data is
when "0000" =>N<="10001000";
when "0001" =>N<="11011011";
when "0010" =>N<="10100010";
when "0011" =>N<="10010010";
when "0100" =>N<="11010001";
when "0101" =>N<="10010100";
when "0110" =>N<="10000100";
when "0111" =>N<="11011010";
when "1000" =>N<="10000000";
when "1001" =>N<="10010000";
when others =>N<="11111111";
end case;
end process;
end Behavioral;
以上为源程序，当inc=‘0’时，应该加1的，但并没有加1，不知何原因？ |
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