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小弟最近在学习VERILOG HDL,<br />想用CPLD代替原有电路中74LS373等一些电路,<br />在迈出第一步时遇到困难啊.......<br />这是我在ISE8.1下写的74LS373模块<br />module AD(D, Q, C);<br /> input [7:0] D;<br /> output [7:0] Q;<br /> input C;<br /> <br /> reg[7:0] ADDR_reg;<br /> always@(negedge C)<br /> begin<br /> ADDR_reg <= D;<br /> end<br /> assign Q = ADDR_reg;<br />endmodule<br />编译出好多警告;<br />1:Clock C appearing in an OFFSET timespec currently must be<br />2:Cannot apply TIMESPEC TS_C = PERIOD:C:20.000nS:HIGH:10.000nS<br />这是为啥捏??<br /><br />感觉这个东东比单片机难好多啊......<br />请大家踊跃帮助,嘿嘿<br /> |
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