//设计描述
`timescale 1ns / 1ps
module compare(equal,a,b);
input a,b;
output equal;
assign equal=(a==b)?1:0;
endmodule
//测试代码
`timescale 1ns / 1ps
`include "./compare.v"
module testcompare_v;
reg a,b;
wire equal;
compare m(.equal(equal),.a(a),.b(b));
initial
begin
a=0;
b=0;
#100 a=0;b=1;
#100 a=1;b=1;
#100 a=1;b=0;
#100 a=0;b=0;
#100 $stop;
end
endmodule
语法没有错，可出来的波形不对，谁知道是什么原因？ |
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