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LIBRARY IEEE;<br />USE IEEE.STD_LOGIC_1164.ALL;<br />USE IEEE.STD_LOGIC_ARITH.ALL;<br /><br />ENTITY cnt6 IS<br /> PORT(reset,en,clk:IN STD_ULOGIC;<br /> carry:OUT STD_ULOGIC;<br /> q:OUT STD_ULOGIC_VECTOR(2 DOWNTO 0);<br />END cnt6;<br /><br />ARCHITECTURE rtl OF cnt6 IS<br /> SIGNALqs:STD_LOGIC_VECTOR(2 DOWNTO 0);<br /> SIGNAL ca:STD_ULOGIC;<br /> BEGIN<br />PROCESS(clk)<br /> VARIABLE q6:INTEGER;<br />BEGIN<br /> IF (clk'EVENT ADN clk='1') THEN<br /> IF(reset='1') THEN<br /> q6:=0;<br />ELSIF (en='1') THEN<br /> IF(q6=5) THEN<br /> q6:=0;<br /> ca<='0';<br /> ELSIF(q6=4) THEN<br /> q6:=q6+1;<br /> ca<='1';<br />ELSE<br /> q6:=q6+1;<br /> ca<='0';<br /> END IF;<br />END IF;<br />END IF;<br /> qs<=CONV_STD_LOGIC_VECTOR(q6,3);<br /> q<=TO_STDULOGICVECTOR(qs);<br />END PROCESS;<br /> PROCESS(ca,en)<br /> BEGIN<br /> carry<=ca AND en;<br /> END PROCESS;<br />END rtl; |
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