高手进来指点下这段程序谢谢!

只看该作者 · 2008-12-9 16:56

FPGA开发板，低价优惠预订中... 高手进来指点下这段程序啊! 谢谢
TABLE
    bit_two,  ab =>out,  bit_two;
    xyab,      1 =>0,    xanb;
    xyab,      2 =>0,    ynab;
    xanb,      3 =>0,    xnanb;
    xanb,      0 =>3,    xyab;
    ynab,      3 =>0,    ynanb;
    ynab,      0 =>3,    xyab;
    xnanb,     2 =>0,    xnab;
    xnanb,     1 =>3,    xyab;

    ynanb,     1 =>0,    yanb;
    ynanb,     2 =>3,    xyab;
    xnab,      0 =>1,    xyab;
    xnab,      3 =>3,    xyab;
    yanb,      0 =>2,    xyab;
    yanb,      3 =>3,    xyab;

END TABLE;
这段程序是什么意思啊能否转换成VHDL啊

先对输入值反向，这样初始输入均为‘00’状态，反向的目的是为了简化状态机的设计，节省资源。若是输入正确正转序列‘11’-‘10’-‘00’-‘01’-‘11，状态机输出10；若是输入正确反转序列‘11’-‘01’-‘00’-‘10’-‘11’，则输出01；若是错误序列，则输出11，