我在用xilinx的FPGA进行相关项目的设计，只有在生成编程文件的时候会有错误报告，我在前面进行布局布线的时候有个错误信息如下 Place:848 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this
design and either lock the clock placement or area locate the logic driven by the clocks so that that the clocks may
be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that
only one clock output signal for any competing Global / Side pair of clocks may enter any region. For further
information see the "Quadrant Clock Routing" section in the Spartan3e Family Datasheet.
The competing Global / Side clock buffers for this device are as follows:
Global : Side
BUFGMUX_X1Y10 : BUFGMUX_X0Y9
BUFGMUX_X1Y10 : BUFGMUX_X3Y9
BUFGMUX_X1Y11 : BUFGMUX_X0Y8
BUFGMUX_X1Y11 : BUFGMUX_X3Y8
BUFGMUX_X2Y10 : BUFGMUX_X0Y7
BUFGMUX_X2Y10 : BUFGMUX_X3Y7
BUFGMUX_X2Y11 : BUFGMUX_X0Y6
BUFGMUX_X2Y11 : BUFGMUX_X3Y6
BUFGMUX_X1Y0 : BUFGMUX_X0Y5
BUFGMUX_X1Y0 : BUFGMUX_X3Y5
BUFGMUX_X1Y1 : BUFGMUX_X0Y4
BUFGMUX_X1Y1 : BUFGMUX_X3Y4
BUFGMUX_X2Y0 : BUFGMUX_X0Y3
BUFGMUX_X2Y0 : BUFGMUX_X3Y3
BUFGMUX_X2Y1 : BUFGMUX_X0Y2
BUFGMUX_X2Y1 : BUFGMUX_X3Y2
哪位大虾帮忙解决一下告诉我是怎么回事怎么解决它，困扰了很长时间了。注我没有添加任何的约束信息。完全是软件默认设置。 |
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