这个分频器的输出是多少？

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worrior_1| 中级技术员

楼主 | 2009-4-6 10:42 | 只看该作者回帖奖励

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分频器, TE, counter, ic, logic

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY counter IS
    GENERIC
    (
        divisor : INTEGER:= 24000000;
        inner_counter_width : INTEGER:= 32;
        unit : STD_LOGIC_VECTOR(3 downto 0):= "1111"
    );

    PORT
    (
        clock : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        counter : BUFFER STD_LOGIC_VECTOR(3 downto 0);
        carrier : BUFFER STD_LOGIC
    );

END counter;

ARCHITECTURE counter_architecture OF counter IS
BEGIN

    PROCESS(clock)
      VARIABLE delay_counter : INTEGER RANGE 0 TO divisor;
    BEGIN
        IF (reset = '1') THEN
            carrier <= '1';
            counter <= "0000";
            delay_counter := 0;
        ELSE
                IF(clock = '1' AND clock'EVENT) THEN
            IF (delay_counter = divisor/2-1) THEN
                carrier <= NOT carrier;
                --var_carrier := NOT var_carrier;
                --carrier <= delay_counter[0];
                    delay_counter := 0;
            ELSE
                delay_counter := delay_counter+1;
                END IF;

            IF (counter = unit) THEN
                counter <= "0000";
            ELSE
                counter <= counter+1;
                END IF;

            END IF;
        END IF;


    END PROCESS;

END counter_architecture;
晶振是66mhz的，divisor是分频系数，carrier是时间输出，我算了算，66/24=2.75hz就是0.36s,那么输出应该是0.36s啊，为什么是1s？

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