verilog-A 是可以写的，也很简单。分频比都是可以设定的。
下面就是代码：
// Frequency dividers
//
// divider1: a ** frequency divider
// divider2: a frequency divider that exhibits gaussian synchronous jitter
//
// Version 1c, 11 February 2008
//
// Ken Kundert
//
// Downloaded from The Designer's Guide (www.designers-guide.org).
// Post any questions to www.designers-guide.org/Forum
`include "disciplines.vams"
//
// This model exhibits no jitter
//
module divider1 (out, in);
output out; voltage out; // output
input in; voltage in; // input (edge triggered)
parameter real vh=+1; // output voltage in high state
parameter real vl=-1; // output voltage in low state
parameter real vth=(vh+vl)/2; // threshold voltage at input
parameter integer ratio=2 from [2:inf); // divide ratio
parameter integer dir=1 from [-1:1] exclude 0;
// dir=1 for positive edge trigger
// dir=-1 for negative edge trigger
parameter real tt=1n from (0:inf); // transition time of output signal
parameter real td=0 from [0:inf); // average delay from input to output
integer count, n;
analog begin
@(cross(V(in) - vth, dir)) begin
count = count + 1; // count input transitions
if (count >= ratio)
count = 0;
n = (2*count >= ratio);
end
V(out) <+ transition(n ? vh : vl, td, tt);
end
endmodule
//
// This model exhibits white synchronous jitter
//
module divider2 (out, in);
output out; voltage out; // output
input in; voltage in; // input (edge triggered)
parameter real vh=+1; // output voltage in high state
parameter real vl=-1; // output voltage in low state
parameter real vth=(vh+vl)/2; // threshold voltage at input
parameter integer ratio=2 from [2:inf); // divide ratio
parameter integer dir=1 from [-1:1] exclude 0;
// dir=1 for positive edge trigger
// dir=-1 for negative edge trigger
parameter real tt=1n from (0:inf); // transition time of output signal
parameter real td=0 from (0:inf); // average delay from input to output
parameter real jitter=0 from [0:td/5); // edge-to-edge jitter
parameter real ttol=1p from (0:td/5); // time tolerance, recommend ttol << jitter
integer count, n, seed;
real dt;
analog begin
@(initial_step) seed = -311;
@(cross(V(in) - vth, dir, ttol)) begin
count = count + 1; // count input transitions
if (count >= ratio)
count = 0;
n = (2*count >= ratio);
dt = jitter*$rdist_normal(seed,0,1); // add jitter
end
V(out) <+ transition(n ? vh : vl, td+dt, tt);
end
endmodule
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楼主
