Located in Shenzhen
Primary Responsibility
Be responsible for physical design of large, complex CMOS chips. Tasks including floor plan, partition, power routing, place & route, static timing analysis, DRC/LVS and other physical verification.
Work with customer design team early in design phase to define good design strategies.
Provide feedback and work closely with product development teams to improve design flow.
Coordinate and work with world wide design teams to ensure on time delivery of design results.
Qualifications
Bachelor degree or above in EE major
Minimum 3 year related experience with a solid IC design and EDA tool background
Solid understanding of deep sub-micron signal integrity issues such a cross-talk, IR drop, etc
Capable of handling multiple tasks at one time
Experienced in place & route, static timing analysis, synthesis
Extensive knowledge and experience with Magma, or Synopsys place & route tools
Extensive knowledge and experience with Synopsys DC, PT and PTSI tool
Experience with Perl, tcl scripting
Good customer communication skill is a must
Good command of English
Good command of Unix
联系邮箱: rabby2003@tom.com |
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