求助，有人用过AD7924吗，用veirlog写过这个片子的时序

只看该作者 · 2013-9-11 11:46

本帖最后由 sulianghe 于 2013-10-10 10:54 编辑

如题

上传的程序

module AD7924(
            clk,
            rst,
            dout,
            din,
            cs,
            sclk,
            AD_data,
            data,
            data_1,
            data_2,
            data_3,
            data_4,
            clk0
            );

input clk;
input rst;

output  sclk;
output  cs;

output  dout;

output  [11:0]  AD_data;

output  [15:0]  data;

output  [11:0]  data_1,data_2,data_3,data_4;

input din;

reg    dout;

reg [15:0]  data;

reg [11:0]  data_1,data_2,data_3,data_4;

reg sclk;

reg  [5:0]  div_cnt ;
reg clk0;

output  clk0;

always@(posedge clk or negedge rst)
if(!rst)
begin
div_cnt <= 0;
clk0 <= 0;
end
else
begin
   if(div_cnt < 25)
   begin
      div_cnt <= div_cnt + 1;
      clk0 <= clk0;
   end
   else
   begin
      div_cnt <= 0;
      clk0 <= ~clk0;
   end
end

PLL U1(
.inclk0(clk),
.c0(AD_clk)
);

reg [5:0]  cnt;
reg       cs;

reg [11:0] AD_data;
reg [3:0]  state;
reg [1:0]  address;
reg [4:0]  i;
reg [15:0] control;
reg [4:0]  delay;

always@(posedge AD_clk or negedge rst)
if(!rst)
begin
cs <= 1;
sclk <= 0;
address <= 0;
i <= 15;
state <= 0;
data <= 0;
control <= {4'b1000,2'b00,10'b11_0000_0000};
end
else
case(state)
0:
  begin
   sclk <= 1;
   cs <= 0;
   state <= 1;
   address <= address + 1'b1;
   case(address)
   2'b00:
      control <= 16'h8330;
   2'b01:
      control <= 16'h8730;
   2'b10:
      control <= 16'h8B30;
   2'b11:
      control <= 16'h8F30;
   endcase
  end
1:
  begin
sclk <= 1;
state <= 2;
  end
2:
  begin
dout <= control[15];
control <= (control<<1);
state <= 3;
  end
3:
  begin
sclk <= 0;
state <= 4;
  end
4:
  begin
data <= (data<<1);
data[0] <= din;
      if(i > 0)
begin
   i <= i - 1;
   state <= 1;
end
else
begin
      i <= 15;
      state <= 5;
   end
  end
5:
  begin
   sclk <= 1;
   cs <= 1;
   AD_data <= data[11:0];
   state <= 0;
   case(data[13:12])
   2'b00:
      data_1 <= AD_data;
   2'b01:
      data_2 <= AD_data;
   2'b10:
      data_3 <= AD_data;
   2'b11:
      data_4 <= AD_data;
   endcase
  end
default:
  begin
   sclk <= 1;
   state <= 0;
   cs <= 1;
  end
endcase

endmodule
//
//
//