这个程序怎么理解啊
11 module ADC0809 ( seven_seg ,ale ,OE ,D ,EOC ,clk ,abc_in ,abc_out ,start ,rst );
12
13 input clk ; //系统时钟
14 input [2:0] abc_in ; //外部控制的通道选择信号
15 input [7:0] D ; //ADC0809传进来的数据
16 input EOC ; //ADC0809转换完成信号标志
17 input rst ; //系统 复位
18
19 output [15:0] seven_seg ; //FPGA给数码管的数据
20 output ale ; //FPGA给ADC0809的地址锁存信号
21 output OE ; //FPGA给ADC0809的使能信号
22 output [2:0] abc_out ; //FPGA给ADC0809的通道选择信号
23 output start ; //ADC0809 转换开始信号
24
25 parameter st0 = 3'b000,
26 st1 = 3'b001,
27 st2 = 3'b010,
28 st3 = 3'b011,
29 st4 = 3'b100,
30 st5 = 3'b101,
31 st6 = 3'b110 ;
32
33 reg [2:0] p_state ;
34 reg [2:0] n_state ;
35 reg ale_r ;
36 reg OE_r ;
37 reg start_r ;
38 reg [7:0] reg1 ;
39 reg [7:0] qq ;
40 wire [2:0] state ;
41
42 assign state = p_state ;
43
44 always @ (posedge clk or negedge rst)
45 begin
46 if ( rst== 1'b0 ) begin
47 p_state <= st0 ;
48 qq <= 8'b0 ;
49
50 end
51 else begin
52 qq <= qq + 1'b1;
53 if ( ( qq >= 8'b0100_0010) && ( clk == 1'b1 ) ) begin
54 qq <= 8'b0;
55 p_state <=#1 n_state;
56 end
57
58 end
59 end
60
61 assign ale = ale_r ;
62 assign OE = OE_r ;
63 assign start = start_r ;
64
65 assign abc_out = abc_in ;
66
67 always @ ( EOC ,p_state )
68 begin
69 case ( p_state )
70 st0 :begin
71 ale_r <= #1 1'b0;
72 start_r <= #1 1'b0;
73 OE_r <= #1 1'b0;
74 n_state <=#1 st1;
75 end
76 st1 :begin
77 ale_r <= #1 1'b1;
78 start_r <= #1 1'b0;
79 OE_r <= #1 1'b0;
80 n_state <=#1 st2;
81 end
82 st2 :begin
83 ale_r <= #1 1'b0;
84 start_r <= #1 1'b1;
85 OE_r <= #1 1'b0;
86 n_state <=#1 st3;
87 end
88 st3 :begin
89 ale_r <= #1 1'b0;
90 start_r <= #1 1'b0;
91 OE_r <= #1 1'b0;
92 if ( EOC == 1'b1 )
93 n_state <=#1 st3;
94 else
95 n_state <=#1 st4;
96
97 end
98 st4 :begin
99 ale_r <= #1 1'b0;
100 start_r <= #1 1'b0;
101 OE_r <= #1 1'b0;
102 if ( EOC == 1'b0 )
103 n_state <=#1 st4;
104 else
105 n_state <=#1 st5;
106 end
107 st5 :begin
108 ale_r <= #1 1'b0;
109 start_r <= #1 1'b0;
110 OE_r <= #1 1'b1;
111 n_state <=#1 st6;
112 end
113 st6 :begin
114 ale_r <= #1 1'b0;
115 start_r <= #1 1'b0;
116 OE_r <= #1 1'b1;
117 reg1 <=#1 D ;
118 n_state <=#1 st0;
119 end
120 default :begin
121 ale_r <= #1 1'b0;
122 start_r <= #1 1'b0;
123 OE_r <= #1 1'b0;
124 n_state <=#1 st0;
125 end
126 endcase
127
128 end
129
130 /******************** 数码管显示译码部分 ***********************************/
131 reg [7:0] Y_r_1;
132 reg [7:0] Y_r_2;
133
134 assign seven_seg[7:0] ={1'b1,(~Y_r_1[6:0])};
135 assign seven_seg[15:8] = {1'b1,(~Y_r_2[6:0])};
136
137 always @(reg1[3:0] )
138 begin
139 Y_r_1 = 7'b1111111;
140 case (reg1[3:0] )
141 4'b0000: Y_r_1 = 7'b0111111; // 0
142 4'b0001: Y_r_1 = 7'b0000110; // 1
143 4'b0010: Y_r_1 = 7'b1011011; // 2
144 4'b0011: Y_r_1 = 7'b1001111; // 3
145 4'b0100: Y_r_1 = 7'b1100110; // 4
146 4'b0101: Y_r_1 = 7'b1101101; // 5
147 4'b0110: Y_r_1 = 7'b1111101; // 6
148 4'b0111: Y_r_1 = 7'b0000111; // 7
149 4'b1000: Y_r_1 = 7'b1111111; // 8
150 4'b1001: Y_r_1 = 7'b1101111; // 9
151 4'b1010: Y_r_1 = 7'b1110111; // A
152 4'b1011: Y_r_1 = 7'b1111100; // b
153 4'b1100: Y_r_1 = 7'b0111001; // c
154 4'b1101: Y_r_1 = 7'b1011110; // d
155 4'b1110: Y_r_1 = 7'b1111001; // E
156 4'b1111: Y_r_1 = 7'b1110001; // F
157 default: Y_r_1 = 7'b0000000;
158 endcase
159 end
160
161 always @( reg1[7:4] )
162 begin
163 Y_r_2 = 7'b1111111;
164 case ( reg1[7:4] )
165 4'b0000: Y_r_2 = 7'b0111111; // 0
166 4'b0001: Y_r_2 = 7'b0000110; // 1
167 4'b0010: Y_r_2 = 7'b1011011; // 2
168 4'b0011: Y_r_2 = 7'b1001111; // 3
169 4'b0100: Y_r_2 = 7'b1100110; // 4
170 4'b0101: Y_r_2 = 7'b1101101; // 5
171 4'b0110: Y_r_2 = 7'b1111101; // 6
172 4'b0111: Y_r_2 = 7'b0000111; // 7
173 4'b1000: Y_r_2 = 7'b1111111; // 8
174 4'b1001: Y_r_2 = 7'b1101111; // 9
175 4'b1010: Y_r_2 = 7'b1110111; // A
176 4'b1011: Y_r_2 = 7'b1111100; // b
177 4'b1100: Y_r_2 = 7'b0111001; // c
178 4'b1101: Y_r_2 = 7'b1011110; // d
179 4'b1110: Y_r_2 = 7'b1111001; // E
180 4'b1111: Y_r_2 = 7'b1110001; // F
181 default: Y_r_2 = 7'b0000000;
182 endcase
183 end
184
185 endmodule
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