用verilog描述ROM遇到问题，请各位帮忙纠错

只看该作者 · 2013-10-14 08:37

源码如下：
module BIOS_ROM(addr[7:0],data[7:0]);

input [7:0]addr;
output[7:0]data;
reg [7:0]rom_data[255:0];

initial $readmemb("test.mif", rom_data);

assign data = rom_data[addr];

endmodule

module CPU_1(led[3:0],clk);

input clk;
output [3:0]led;
wire [7:0]data1;
wire [7:0]addr1;

parameter times = 23'd 5_000_000;
reg [31:0]T,timer;
reg [7:0]addr2;

BIOS_ROM ROM1(addr1[7:0],data1[7:0]);

assign led = data1 >> 4;
assign addr1 = addr2;

always@(posedge clk)
begin
if(T == times)
begin
T <= 32'd0;
timer <= ~timer;
end
else
T <= T + 32'd1;
end

always@(posedge timer)
begin
addr2 <= addr2 + 1'b1;
end

endmodule

Error (10170): Verilog HDL syntax error at test.mif(1) near text -
Error: Can't elaborate user hierarchy "BIOS_ROM:ROM1"