bits 31:24 MEMHIZx:Defines the number of HCLK (+1 only for NAND) clock cycles during which the databus is
kept in HiZ after the start of a PC Card/NAND Flash write access to common memory space
on socket x. Only valid for write transaction:
又看了几家的NAND芯片datasheet,包括Hynix, Samsung, Micron,以及一个台厂。他们的时序基本上都是一样的,访问过程包括command latch cycle, address latch cycle, input data cycle, serial data access after read。这四种可能情况下面,都没有提出HiZ高阻态的要求。