|
This document describes theoperation of the software-programmable phase-locked loop (PLL) controller inthe TMS320C6474 digital signal processors (DSPs). The PLL controller offersflexibility and convenience by way of software-configurable multiplier anddividers to modify the input signal internally. The resulting clock outputs arepassed to the C6474 DSP core, peripherals, and other modules.
| 
楼主
标题置顶
标题高亮
