寄存器设置问题

只看该作者 · 2013-11-26 21:32

想用DCO + FLL来得到较为稳定的5MHz，所以设置了一下寄存器，请大侠看一下这样的设置是不是有问题啊？

只看该作者 · 2013-11-26 21:32

void Clock_Initial(void){
      WDTCTL = WDTPW + WDTHOLD;
      P2SEL |= BIT2;
      P2DIR |= BIT2;                         // Test SMCLK Output P2.2

      P5SEL |= BIT4 + BIT5;                                        // Port select XT1
      REFCTL0 &= ~REFMSTR;

      UCSCTL6 &= ~(XT1OFF);                   // XT1 On
      UCSCTL6 |= XCAP_3;                      // Internal load cap

      // Loop until XT1 fault flag is cleared
      do
      {
      UCSCTL7 &= ~XT1LFOFFG;                // Clear XT1 fault flags
      }while (UCSCTL7&XT1LFOFFG);             // Test XT1 fault flag

      // Initialize DCO to 5MHz
      __bis_SR_register(SCG0);                // Disable the FLL control loop
      UCSCTL0 = 0x0000;                      // Set lowest possible DCOx, MODx
      UCSCTL1 = DCORSEL_5;                                        // 2.5MHz - 6MHz
      UCSCTL2 = FLLD_0 + 152;                   // Set DCO Multiplier for 5MHz
                                                // (N + 1) * FLLRef = Fdco
                                                // (152 + 1) * 32768 = 5MHz
                                                // Set FLL Div = fDCOCLK/1
      UCSCTL3 = SELREF_2 + FLLREFDIV_0;                // Reference of FLL select REFOCLK, fFLLREFCLK/1
      UCSCTL4 = SELA_3 + SELS_3 + SELM_3;                // SMCLK = ADCLK = MCLK = DCOCLK
      UCSCTL5 = DIVPA_0 + DIVA_0 + DIVS_0 + DIVM_0; //

      __bic_SR_register(SCG0);                // Enable the FLL control loop

      // 32 x 32 x 5 MHz / 32,768 Hz = 156250 = MCLK cycles for DCO to settle
      __delay_cycles(156250);

      do
      {
         UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);       // Clear XT2,XT1,DCO fault flags
         SFRIFG1 &= ~OFIFG;                                     // Clear fault flags
      }while (SFRIFG1 & OFIFG);                         // Test oscillator fault flag
}

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