[技术问答] 【七，八楼已更正说明】为什么工程配置时设置频率为50MHZ

uint32_t SystemCoreClock  = __HSI;              /*!< System Clock Frequency (Core Clock) */

uint32_t CyclesPerUs      = (__HSI / 1000000);  /*!< Cycles per micro second             */

uint32_t PllClock         = __HSI;              /*!< PLL Output Clock Frequency    

#define __XTAL      (12000000UL)    /*!< External Crystal Clock Frequency     */

#define __IRC22M    (22118400UL)    /*!< Internal 22M RC Oscillator Frequency */

#define __IRC10K    (10000UL)       /*!< Internal 10K RC Oscillator Frequency */

#define __HSI       (50000000UL)    /*!< PLL default output is 48MHz@12M X'tal or 48.065MHz@22.1184MHz IRC */

#if (__XTAL == 12000000)

#define SYSCLK_PLLCON_50MHz_XTAL   (SYSCLK_PLLCON_FIN_XTAL | SYSCLK_PLLCON_NR(3) | SYSCLK_PLLCON_NF( 25) | SYSCLK_PLLCON_NO_2) /*!< Predefined PLLCON setting for 50MHz PLL output with 12MHz X'tal */

#define SYSCLK_PLLCON_48MHz_XTAL   (SYSCLK_PLLCON_FIN_XTAL | SYSCLK_PLLCON_NR(7) | SYSCLK_PLLCON_NF(112) | SYSCLK_PLLCON_NO_4) /*!< Predefined PLLCON setting for 48MHz PLL output with 12MHz X'tal */

#define SYSCLK_PLLCON_36MHz_XTAL   (SYSCLK_PLLCON_FIN_XTAL | SYSCLK_PLLCON_NR(7) | SYSCLK_PLLCON_NF( 84) | SYSCLK_PLLCON_NO_4) /*!< Predefined PLLCON setting for 36MHz PLL output with 12MHz X'tal */

#define SYSCLK_PLLCON_32MHz_XTAL   (SYSCLK_PLLCON_FIN_XTAL | SYSCLK_PLLCON_NR(6) | SYSCLK_PLLCON_NF( 64) | SYSCLK_PLLCON_NO_4) /*!< Predefined PLLCON setting for 32MHz PLL output with 12MHz X'tal */

#else

Reset_Handler   PROC

                EXPORT  Reset_Handler             [WEAK]

                IMPORT  SystemInit

                IMPORT  __main

void SystemInit(void)

{

#ifdef INIT_SYSCLK_AT_BOOTING

    int32_t i32TimeoutCnt;

    uint32_t u32HclkSelect;

    int8_t i8IsPllEn;



    PllClock = 0;

    i8IsPllEn = 0;

    u32HclkSelect = SYSCLK->CLKSEL0 & SYSCLK_CLKSEL0_HCLK_S_Msk;

    if(u32HclkSelect == SYSCLK_CLKSEL0_HCLK_XTAL)

    {

        /* Set to 50MHz system clock frequency when clock source is from external 12MHz */

        SYSCLK->PLLCON = SYSCLK_PLLCON_50MHz_XTAL;       

        

        /* Waiting for PLL ready */

        i32TimeoutCnt = (__XTAL / 1000); /* Timeout is about 1ms */

        while((SYSCLK->CLKSTATUS & SYSCLK_CLKSTATUS_PLL_STB_Msk) == 0 )

        {

            if(i32TimeoutCnt-- <= 0)

                break;    

        }



        i8IsPllEn = 1;

    }

    else if(u32HclkSelect == SYSCLK_CLKSEL0_HCLK_IRC22M)

    {

        /* Set to 50.1918MHz system clock frequency when clock source is from internal 22.1184MHz RC clock */

        SYSCLK->PLLCON = SYSCLK_PLLCON_50MHz_IRC22M;       

        

        /* Waiting for PLL ready */

        i32TimeoutCnt = (__IRC22M / 1000); /* Timeout is about 1ms */

        while((SYSCLK->CLKSTATUS & SYSCLK_CLKSTATUS_PLL_STB_Msk) == 0 )

        {

            if(i32TimeoutCnt-- <= 0)

                break;    

        }



        i8IsPllEn = 1;

    }



    if(i8IsPllEn)    

    {

        /* Set PLL as HCLK clock source (HCLK_S is locked setting)*/

        SYS_UnlockReg();

        SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_PLL;

        SYS_LockReg();

    }

#endif

}