本帖最后由 xiantingfeng 于 2013-12-17 10:09 编辑
add, mti, ram这些IP核，在ISE中实现，map的时候， 被移除，无法实现其功能。
前期通过了modelsim仿真，ISE的综合，在planahead中可以看到各IP核的信息，编写了UCF。实现时，翻译通过，但映射时提示被移除。ddr2 ram的UCF利用了user design中的UCF，这个在map后模块仍然存在。
可能是因为没有作为输出信号，add, mti IP的输出结果在程序内部使用的，但应该不至于吧。
clk信号分配了芯片引脚，是不是clk信号给错，我在planahead中，找到一个GCLK引脚，在UCF中分配，这会不会有问题，是不是需要DCM之类。不知道怎么回事。
如The signal "add1/sig000005cc" is loadless and has been removed.提示是说 sourceless or loadless signals, and VCC or ground connections。
具体map report 如下：
Section 4 - Removed Logic Summary
---------------------------------
71744 block(s) removed 2 block(s) optimized away
73965 signal(s) removed 24 Block(s) redundant
The trimmed logic report below shows the logic removed from your design due to sourceless or loadless signals, and VCC or ground connections. If the removal of a signal or symbol results in the subsequent removal of an additional signal or symbol, the message explaining that second removal will be indented. This indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
Loadless block "add1/blk000002b3" (XOR) removed.
The signal "add1/sig000005cc" is loadless and has been removed.
Loadless block "add1/blk000002b5" (MUX) removed.
The signal "add1/sig000005d5" is loadless and has been removed.
Loadless block "div1/blk00001654" (MUX) removed.
等等，，，，
********* The signal "div1/sig00001525" is loadless and has been removed.
********* Loadless block "div1/blk00001652" (MUX) removed.
********* The signal "div1/sig00001524" is loadless and has been removed.
下面还有很多这个提示。
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