推荐写法：- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_unsigned.all;
- entity addr_a is
- port( clk :in std_logic;
- load:in std_logic;
- m :in std_logic_vector(7 downto 0);
- addr:out std_logic_vector(23 downto 0)
-
- );
- end;
-
- ARCHITECTURE one of addr_a is
-
-
- signal dlta:std_logic_vector(23 downto 0):=(others=>'0');
- signal sum:std_logic_vector(23 downto 0):=(others=>'0');
-
- signal load_d1: std_logic;
- signal load_d2: std_logic;
- signal load_up: std_logic;
-
- begin
- process(clk)
- begin
- if rising_edge(clk) then
- load_d1<=load;
- load_d2<=load_d1;
- end if;
- end process;
- load_up<=load_d1 and (not load_d2);
- process(clk)
- begin
- if rising_edge(clk) then
- if load_up='1' then
- dlta(7 downto 0)<=m;
- dlta(23 downto 8) <=(others=>'0');
- end if;
- end if;
- end process;
-
-
- process(clk)
- begin
- if rising_edge(clk) then
- sum <= dlta + sum;
- end if;
- end process;
- addr<=sum;
- end one;
| 
