想得到如图所示的波形,最后两行:上面是PWM输入,下面是程序处理后的输出!
想实现的功能:在PWM输入的上升沿固定延时4us,下降沿跟随PWM输入!
我想谈谈自己的想法:
方案一:把PWM输入整体右移4us,然后与原pwm波形相与得到所需的波形;
方案二:检测pwm输入的上升沿,检测到上升沿开始触发计数器计数到4us,计数器清0,计数期间输出0;其它时间原样输出pwm;
这里有个问题:方案二:pwm检测期间,如何触发定时器啊,需要锁存检测到的pwm上升沿信号吗?因为CLK上升沿开始检测,检测到PWM上升沿以后,高电平期间的检测rising_edge=0;
以下是我的代码,总感觉代码里面有些问题,敬请高手指正:
`define DELAY 3
module deathtime1(dt_pwm,clk,pwm,rst);
output dt_pwm;
input clk,pwm,rst;
reg dt_pwm; //最终输出
reg r0_pwm,r1_pwm;
reg counter,clr,flag;
wire rising_edge;
always@(posedge clk or negedge rst) //2位移位寄存器寄存
begin
if(!rst)
begin
r0_pwm<=1'bx;
r1_pwm<=1'bx;
end
else
begin
r0_pwm<=pwm;
r1_pwm<=r0_pwm;
end
end
assign rising_edge=~r0_pwm&r1_pwm; //判断PWM上升沿
always@(rising_edge or clr) //锁存器锁存上升沿,得到计数使能flag
begin
if(!clr)
flag<=0;
if(rising_edge)
flag<=1;
end
always@(posedge clk or negedge rst) //计数器counter
if(!rst)
counter<=0;
else
begin
if(flag)
begin
if(counter>`DELAY)
begin
counter<=0;
clr<=0;
end
else
counter<=counter+1;
end
else
counter<=0;
end
always@(posedge clk or negedge rst)
begin
if(!rst)
dt_pwm<=0;
else
if((counter<=`DELAY)&&(counter>=1))
dt_pwm<=0;
else
dt_pwm<=pwm;
end
endmodule |