请大家帮忙看看为什么modelsim仿真不出现波形框呢？

只看该作者 · 2014-1-14 11:22

这是一个乘法器的模块
module multiplier_module(
clk,
rstn,
done_sig,
multiplier,
multiplicand,
product,
start_sig
);
input start_sig;
input clk;
input rstn;
input [7:0]multiplier;
input [7:0]multiplicand;
output done_sig;
output [15:0]product;
reg isdone;
reg [1:0]i;
reg [7:0]mer;
reg [7:0]mnd;
reg [15:0]temp;
reg isneg;

always @(posedge clk or negedge rstn)
if(!rstn)
begin
i<=2'd0;
isdone<=1'b0;
mer<=8'd0;;
mnd<=8'd0;
temp<=8'd0;
isneg<=1'b0;
end
else if(start_sig)
case(i)
0:
begin
isneg<=multiplicand[7]^multiplier[7];
mer<=multiplier[7]?(~multiplier+1'b1):multiplier;
mnd<=multiplicand[7]?(~multiplicand+1'b1):multiplicand;
//{mer,mnd}<=mer<mnd?{mnd,mer}:{mer,mnd};
temp<=16'd0;
i<=i+1'b1;
end
1:
if(mnd==0)
i<=i+1'b1;
else
begin
temp<=temp+mer;
mnd<=mnd-1'b1;
end
2:
begin
isdone<=1'b1;
i<=i+1'b1;
end
3:
begin
isdone<=1'b0;
i<=2'b0;
end
endcase

assign done_sig=isdone;
assign product=isneg?(~temp+1'b1):temp;

endmodule
============================================================
这是testbench：
`timescale 1 ps/ 1 ps
module multiplier_module_simulation();

reg clk;
   reg rstn;

   reg start_sig;
reg [7:0] multiplicand;
reg [7:0] multiplier;

wire done_sig;
wire [15:0]product;

   /***********************************/

initial
begin

      rstn = 0; #10; rstn = 1;
      clk = 1; forever #10 clk = ~clk;

   end

   /***********************************/

multiplier_module U1
   (
      .clk(clk),
   .rstn(rstn),
   .start_sig(start_sig),
      .multiplicand(multiplicand),
      .multiplier(multiplier),
   .done_sig(done_sig),
      .product(product)
);

   /***********************************/

   reg [3:0]i;

always @ ( posedge clk or negedge rstn )
      if( !rstn )
         begin
      i <= 4'd0;
      start_sig <= 1'b0;
            multiplicand <= 8'd0;
            multiplier <= 8'd0;
         end
   else
      case( i )

      0: // Multiplicand = 10 , Multiplier = 2
   if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; end
   else begin multiplicand <= 8'd10; multiplier <= 8'd2; start_sig <= 1'b1; end

   1: // Multiplicand = 2 , Multiplier = 10
   if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; end
   else begin multiplicand <= 8'd2; multiplier <= 8'd10; start_sig <= 1'b1; end

   2: // Multiplicand = 11 , Multiplier = -5
   if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; end
   else begin multiplicand <= 8'd11; multiplier <= 8'b11111011; start_sig <= 1'b1; end

      3: // Multiplicand = -5 , Multiplier = -11
   if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; end
   else begin multiplicand <= 8'b11111011; multiplier <= 8'b11110101; start_sig <= 1'b1; end
      4:
   begin i <= 4'd4; end

endcase

endmodule

仿真只到这一步就不再出现其他框了。这是为什么呢？