msp430外界32.768K时钟，

只看该作者 · 2014-2-21 11:07

void init_sys_clock(void)
{
   P5SEL |= 0x03;                         // Enable XT1 pins
   UCSCTL6 |= XCAP_3;                      // Internal load cap(12pF)

   // Loop until XT1 fault flag is cleared
   do
   {
      UCSCTL7 &= ~XT1LFOFFG;                // Clear XT1 fault flags
   }while (UCSCTL7&XT1LFOFFG);             // Test XT1 fault flag

   // Initialize DCO to 2.45MHz
   __bis_SR_register(SCG0);                // Disable the FLL control loop
   UCSCTL0 = 0x0000;                      // Set lowest possible DCOx, MODx
   UCSCTL1 = DCORSEL_5;                   // Set RSELx for DCO = 4.9 MHz
   UCSCTL2 = FLLD_0 + 511;                   // Set DCO Multiplier for 16.777216MHz
                                             // (N + 1) * FLLRef = Fdco
                                             // (511 + 1) * 32768 = 16.777216MHz
                                             // Set FLL Div = fDCOCLK/1
   __bic_SR_register(SCG0);                // Enable the FLL control loop

   // Worst-case settling time for the DCO when the DCO range bits have been
   // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
   // UG for optimization.
   // 32 x 32 x 16.777216MHz / 32,768 Hz = 524288 = MCLK cycles for DCO to settle
   __delay_cycles(524288);

   // Loop until XT1,XT2 & DCO fault flag is cleared
   do
   {
      UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
                                             // Clear XT2,XT1,DCO fault flags
      SFRIFG1 &= ~OFIFG;                   // Clear fault flags
   }while (SFRIFG1&OFIFG);                // Test oscillator fault flag

}
这样初始化之后，ACLK  MCLK SCLK各是多少，  也请大神推荐一个关于时钟系统的好**