module dj (clk_27m,rst_n,fangxiang,sudu,outf,outs,count_gd,HEX1,HEX2,HEX3,HEX4);
input clk_27m;
input rst_n;
input fangxiang;
input sudu;
input count_gd;
output outf,outs;
output [6:0]HEX1,HEX2,HEX3,HEX4;
reg outf;
wire outs;
reg en;
/************************************/
/*************************************/
always @ ( negedge rst_n or posedge clk_27m)
if (!rst_n)
outf<=0;
else outf<=(fangxiang?1:0);
/*************************************/
reg delay;
always @ (sudu)
case (sudu)
4'b0001:delay<=9'd100;
4'b0011:delay<=9'd200;
4'b0111:delay<=9'd300;
4'b1111:delay<=9'd400;
endcase
/*************************************/
speed_control u1(.clk(clk_27m),.rst(rst_n),.yanchi(delay),.shuchu(outs));
/*************************************/
reg count;
always @ (posedge clk_27m )
if (!rst_n) count<=0;
else if (count==27000000)
begin en<=1;count<=0;end
else
begin en<=0;count<=count+1;end
/*************************************/
reg [3:0] cs_ge;
reg [3:0] cs_shi;
reg [3:0] cs_bai;
reg [3:0] cs_qian;
always @ (negedge count_gd)
if (!rst_n)
begin
cs_ge <= 4'd0;
cs_shi <= 4'd0;
cs_bai <= 4'd0;
cs_qian <= 4'd0;
end
else if (en)
begin
cs_ge <= 4'd0;
cs_shi <= 4'd0;
cs_bai <= 4'd0;
cs_qian <= 4'd0;
end
else
begin
if(cs_ge==4'd9 && cs_shi<4'd10 && cs_bai<4'd10 && cs_qian<4'd10)
begin
cs_ge <= 4'd0;
cs_shi <= cs_shi + 4'd1;
if(cs_shi == 4'd9 && cs_bai<4'd10 && cs_qian<4'd10)
begin
cs_shi <= 4'd0;
cs_bai <= cs_bai + 4'd1;
end
if(cs_bai == 4'd9 && cs_qian<4'd10)
begin
cs_bai <= 4'd0;
cs_qian <= cs_qian + 4'd1;
end
end
else if(cs_qian==4'd10 && cs_bai==4'd9 && cs_shi==4'd9 && cs_ge==4'd9)
begin
cs_ge <= 4'd0;
cs_shi <= 4'd0;
cs_bai <= 4'd0;
cs_qian <= 4'd0;
end
else
begin
cs_ge <= cs_ge + 4'd1;
end
end
/***************************************/
reg [6:0]HEX01,HEX02,HEX03,HEX04;
always @ (cs_qian)
case (cs_qian)
4'd0:HEX01=7'd192;
4'd1:HEX01=7'd249;
4'd2:HEX01=7'd164;
4'd3:HEX01=7'd176;
4'd4:HEX01=7'd153;
4'd5:HEX01=7'd146;
4'd6:HEX01=7'd130;
4'd7:HEX01=7'd1248;
4'd8:HEX01=7'd128;
4'd9:HEX01=7'd144;
endcase
always @ (cs_bai)
case (cs_bai)
4'd0:HEX02=7'd192;
4'd1:HEX02=7'd249;
4'd2:HEX02=7'd164;
4'd3:HEX02=7'd176;
4'd4:HEX02=7'd153;
4'd5:HEX02=7'd146;
4'd6:HEX02=7'd130;
4'd7:HEX02=7'd1248;
4'd8:HEX02=7'd128;
4'd9:HEX02=7'd144;
endcase
always @ (cs_shi)
case (cs_shi)
4'd0:HEX03=7'd192;
4'd1:HEX03=7'd249;
4'd2:HEX03=7'd164;
4'd3:HEX03=7'd176;
4'd4:HEX03=7'd153;
4'd5:HEX03=7'd146;
4'd6:HEX03=7'd130;
4'd7:HEX03=7'd1248;
4'd8:HEX03=7'd128;
4'd9:HEX03=7'd144;
endcase
always @ (cs_ge)
case (cs_ge)
4'd0:HEX04=7'd192;
4'd1:HEX04=7'd249;
4'd2:HEX04=7'd164;
4'd3:HEX04=7'd176;
4'd4:HEX04=7'd153;
4'd5:HEX04=7'd146;
4'd6:HEX04=7'd130;
4'd7:HEX04=7'd1248;
4'd8:HEX04=7'd128;
4'd9:HEX04=7'd144;
endcase
assign HEX1=HEX01;
assign HEX2=HEX02;
assign HEX3=HEX03;
assign HEX4=HEX04;
/***************************************/
endmodule
module speed_control (clk,rst,yanchi,shuchu);
input clk;
input rst;
input yanchi;
output shuchu;
wire shuchu;
reg shuch;
reg wahaha;
always@(posedge clk)
if (!rst)
shuch<=0;
else if(wahaha==yanchi)
begin shuch<=1;wahaha=0;end
else begin shuch<=0;wahaha<=wahaha+1;end
assign shuchu=shuch;
endmodule
这是测试的脚本
initial
begin
rst_n=0;
#10 rst_n=1;
fangxiang=1;
clk_27m=0;
count_gd=0;
sudu=4'b0001;
end
always
begin
#10 clk_27m=~clk_27m;
#10 count_gd=~count_gd;
end
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