// Setup TBCLK
// TBCLK=SYSCLKOUT/(HSPCLKDIV*CLKDIV)=60M/(2*2)=15M
// PWM FREQUENCY=15M/(EPWM1_TIMER_TBPRD*2)=15M/(750*2)=10K
EPwm1Regs.TBCTL.bit.CTRMODE = 2; // up down
EPwm1Regs.TBPRD = 750; / t period
EPwm1Regs.TBCTL.bit.PHSEN = 0; // Disable phase loading Clearing the TBCTL[PHSEN] bit configures the ePWM to ignore the synchronization input pulse
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV =1; // /2
EPwm1Regs.TBCTL.bit.CLKDIV = 1; // /2
// Setup shadow register load on PERIOD
// EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; //Shadow mode
// EPwm1Regs.CMPCTL.bit.LOADAMODE = 1; //Load on CTR = PRD
// Set Compare values
// EPwm1Regs.CMPA.half.CMP_A = 300; // Set Compare A value
// EPwm1Regs.CMPB = 300; // Set Compare B value
EPwm1Regs.ETSEL.bit.INTSEL = 2; // period interrupt TBCTR = TBPRD
EPwm1Regs.ETSEL.bit.INTEN = 1; // enable interrupt
EPwm1Regs.ETPS.bit.INTPRD = 1; // Generate INT on first event
}
interrupt void eva_time1_isr(void)
{
// Clear INT flag for this timer
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
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