又来了...麻烦哥们儿帮我看看...altera EPM240 CPLD程序问题

只看该作者 · 2014-4-2 11:32

现在要做一个只用非门来控制脉冲延时宽度的电路，不需要CLK，现在程序前面的都可以了，只有最后判断quench下降沿触发出一个reset2信号时出了问题，这样出来的reset2信号从头到尾都是高电平...reset2信号的非门延时我还没有加，是程序有什么问题么？麻烦帮我看看，哥们儿们，小弟谢过！

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity not_del is
port(
tr_in:in std_logic;
Q: buffer std_logic;
reset,reset1:buffer std_logic;
reset2:out std_logic;
quench:buffer std_logic;
Gate_in:in std_logic
);
end not_del;

architecture behavioral of not_del is
attribute syn_keep:boolean;
signal tr,gate:std_logic;
signal sig1,sig2,sig3,sig4,sig5,sig6,sig7,sig8,sig9,sig10,sig11,sig12,sig13,sig14,sig15,sig16,sig17,sig18,sig19,sig20,sig21,sig22,sig23,sig24:std_logic;
attribute syn_keep of sig1,sig2,sig3,sig4,sig5,sig6,sig7,sig8,sig9,sig10,sig11,sig12,sig13,sig14,sig15,sig16,sig17,sig18,sig19,sig20,sig21,sig22,sig23,sig24:signal is true;
begin
process(tr_in)
begin
gate<=not(Gate_in);
tr<=tr_in and gate;
end process;

process(tr)
begin
sig1<=not(tr);
sig2<=not(sig1);
sig3<=not(sig2);
sig4<=not(sig3);
sig5<=not(sig4);
sig6<=not(sig5);
sig7<=not(sig6);
sig8<=not(sig7);
sig9<=not(sig8);
sig10<=not(sig9);
sig11<=not(sig10);
sig12<=not(sig11);
sig13<=not(sig12);
sig14<=not(sig13);
sig15<=not(sig14);
sig16<=not(sig15);
sig17<=not(sig16);
sig18<=not(sig17);
sig19<=not(sig18);
sig20<=not(sig19);
sig21<=not(sig20);
sig22<=not(sig21);
sig23<=not(sig22);
sig24<=not(sig23);
end process;

process(tr,reset)
begin
reset<=sig18;
reset1<=sig24;
if(reset='1')then
Q<='0';
elsif(reset1='1')then
quench<='0';
elsif(tr'EVENT and tr='1')then
Q<= '1';
quench<='1';
end if;
end process;

process(quench)
begin
if(quench'EVENT and quench='0')then
reset2<='1';
end if;
end process;

end behavioral;