仅供参考
module test(rst,clk,ek,lk);
input rst,clk;
input [15:0] ek;
output reg [15:0] lk;
reg [15:0] Data_org [68:0];
reg [15:0] cnt;
generate
genvar i; //generate 69 instance
for(i=0; i<69; i=i+1) begin: modulename
always@(posedge clk or posedge rst)
if(rst)
Data_org[i]<=16'h0;
else
Data_org[i]<=ek+i;
end
endgenerate
always@(posedge clk or posedge rst)
if(rst)
cnt<=16'd0;
else
cnt<=cnt+1'b1;
always@(posedge clk or posedge rst)
if(rst)
lk<=16'd0;
else
lk<=Data_org[cnt];
endmodule
|
楼主
