//SDRAM.ini
/******************************************************************************/
/* Dbg_RAM.ini: Initialization Script for Debugging in SDRAM */
/******************************************************************************/
/* This file is part of the uVision/ARM development tools. */
/* Copyright (c) 2011 Keil Software. All rights reserved. */
/* This software may only be used under the terms of a valid, current, */
/* end user licence from KEIL for a compatible version of KEIL software */
/* development tools. Nothing else gives you the right to use this software. */
/******************************************************************************/
DEFINE INT Entry;
DEFINE LONG GCR_BA;
DEFINE LONG CLK_BA;
DEFINE LONG SDIC_BA;
DEFINE LONG GP_BA;
Entry = 0x00008000;
GCR_BA = 0xB0000000;
CLK_BA = 0xB0000200;
SDIC_BA = 0xB0003000;
GP_BA = 0xB8001000;
FUNC void Clock_Setup (void)
{
}
FUNC void SDRAM_Setup(void)
{
_WDWORD(0xb0003000, 0x00130456); // SDOPM Init DDR
_WDWORD(0xb0003030, 0x00001010); // DQSODS
_WDWORD(0xb0003010, 0x00000005); // SDSIZE0
_WDWORD(0xb0003004, 0x00000021); // SDCMD
_WDWORD(0xb0003004, 0x00000023); // SDCMD
_WDWORD(0xb0003004, 0x00000027); // SDCMD
_WDWORD(0xb000301C, 0x00001002); // SDEMR
_WDWORD(0xb0003018, 0x00000122); // SDMR
_WDWORD(0xb0003004, 0x00000027); // SDCMD
_WDWORD(0xb0003004, 0x0000002B); // SDCMD
_WDWORD(0xb0003004, 0x0000002B); // SDCMD
_WDWORD(0xb0003018, 0x00000022); // SDMR
_WDWORD(0xb0003004, 0x00000020); // SDCMD
_WDWORD(0xb0003034, 0x00AAAA00); // CKDQSDS
_WDWORD(0xb0003008, 0x0000805A); // SDREF
_WDWORD(0xb00000A0, 0x00000000); // MISCPCR
_WDWORD(0xb0000224, 0x0000447E); // UPLLCON PLL=192MHz
_WDWORD(0xb000020C, 0x00000018); // CLKDIV0 Divider
_WDWORD(0xb000021C, 0x00000000); // CLKDIV4
_WDWORD(0xb0003028, 0x094E7549); // SDTIME Sdram Timing
_sleep_(10);
_WDWORD(0xb8001010, 0x00000008); // GPIOB_OMD PB3=OUTPUT
_WDWORD(0xb8001018, 0x00000008); // GPIOB_DOUT PB3=HIGH
_sleep_(10);
}
FUNC void Remap (void)
{
}
FUNC void Download (void)
{
exec("load %L incremental");
}
FUNC void PC_Setup (void)
{
PC = Entry;
}
FUNC void GoMain (void)
{
exec("g,main");
}
//Clock_Setup();
SDRAM_Setup();
//Remap();
Download();
PC_Setup();
GoMain();
//main.c文件
#include <stdio.h>
#include "wblib.h"
#define DebugCom 0x100
void Delay(UINT32 k)
{
volatile int j=k*36000;
while(j--);
}
void InitDebugCom(void)
{
WB_UART_T *uart;
//Nornal Speed UART
outp32(REG_GPAFUN, inp32(REG_GPAFUN) | (MF_GPA11 | MF_GPA10));
outp32(REG_APBCLK, inp32(REG_APBCLK) | UART1_CKE);
uart->uiFreq = (((inp32(REG_CHIPCFG)&0xC)==0x8)?12000:27000)*1000; /*Use external clock*/
uart->uiBaudrate = 115200;
uart->uiDataBits = WB_DATA_BITS_8;
uart->uiStopBits = WB_STOP_BITS_1;
uart->uiParity = WB_PARITY_NONE;
uart->uiRxTriggerLevel = LEVEL_1_BYTE;
/* Reset the TX/RX FIFOs */
outpw(REG_UART_FCR+DebugCom, 0x07);
/* Setup baud rate */
outpw(REG_UART_BAUD+DebugCom, ((0x30<<24)|((uart->uiFreq / uart->uiBaudrate)-2)));
/* Set the modem control register. Set DTR, RTS to output to LOW,
and set INT output pin to normal operating mode */
//outpb(UART_MCR, (WB_DTR_Low | WB_RTS_Low | WB_MODEM_En));
/* Setup parity, data bits, and stop bits */
outpw(REG_UART_LCR+DebugCom,(uart->uiParity | uart->uiDataBits | uart->uiStopBits));
/* Timeout if more than ??? bits xfer time */
outpw(REG_UART_TOR+DebugCom, 0x80+0x20);
/* Setup Fifo trigger level and enable FIFO */
outpw(REG_UART_FCR+DebugCom, uart->uiRxTriggerLevel|0x01);
}
int fputc(int ch, FILE *f)
{
/* Wait until the transmitter buffer is empty */
while (!(inpw(REG_UART_FSR+DebugCom)&0x400000));
/* Transmit the character */
outpb(REG_UART_THR+DebugCom, ch);
return ch;
}
int fgetc(FILE *f)
{
while((inpw(REG_UART_ISR+DebugCom)&0x01)==0);
return(inpb(REG_UART_RBR+DebugCom));
}
int main(void)
{
int i=0;
InitDebugCom();
printf("\n\r\n\r");
printf("*** 9G-N32905 V1.00 Build by yuanxihua@21cn.com on ("__DATE__ " - " __TIME__ ")\n\r");
printf("*** 9G-N32905 V1.00 Running ...\n\r\n\r");
outp32(REG_GPIOC_OMD,0x0000FFFF);
outp32(REG_GPIOE_OMD,0x0000FFFF);
while(1)
{
printf("run times %d\n\r",i++);
outp32(REG_GPIOC_DOUT,0x0000FFFF);
outp32(REG_GPIOE_DOUT,0x0000FFFF);
Delay(500);
outp32(REG_GPIOC_DOUT,0x00000000);
outp32(REG_GPIOE_DOUT,0x00000000);
Delay(500);
}
}
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